Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/armada-xp-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP evaluation board
   3  * (DB-78460-BP)
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 /dts-v1/;
  17 /include/ "armada-xp-mv78460.dtsi"
  18
  19 / {
  20         model = "Marvell Armada XP Evaluation Board";
  21         compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,115200 earlyprintk";
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 reg = <0x00000000 0x80000000>; /* 2 GB */
  30         };
  31
  32         soc {
  33                 serial@d0012000 {
  34                         clock-frequency = <250000000>;
  35                         status = "okay";
  36                 };
  37                 serial@d0012100 {
  38                         clock-frequency = <250000000>;
  39                         status = "okay";
  40                 };
  41                 serial@d0012200 {
  42                         clock-frequency = <250000000>;
  43                         status = "okay";
  44                 };
  45                 serial@d0012300 {
  46                         clock-frequency = <250000000>;
  47                         status = "okay";
  48                 };
  49
  50                 sata@d00a0000 {
  51                         nr-ports = <2>;
  52                         status = "okay";
  53                 };
  54
  55                 mdio {
  56                         phy0: ethernet-phy@0 {
  57                                 reg = <0>;
  58                         };
  59
  60                         phy1: ethernet-phy@1 {
  61                                 reg = <1>;
  62                         };
  63
  64                         phy2: ethernet-phy@2 {
  65                                 reg = <25>;
  66                         };
  67
  68                         phy3: ethernet-phy@3 {
  69                                 reg = <27>;
  70                         };
  71                 };
  72
  73                 ethernet@d0070000 {
  74                         status = "okay";
  75                         phy = <&phy0>;
  76                         phy-mode = "rgmii-id";
  77                 };
  78                 ethernet@d0074000 {
  79                         status = "okay";
  80                         phy = <&phy1>;
  81                         phy-mode = "rgmii-id";
  82                 };
  83                 ethernet@d0030000 {
  84                         status = "okay";
  85                         phy = <&phy2>;
  86                         phy-mode = "sgmii";
  87                 };
  88                 ethernet@d0034000 {
  89                         status = "okay";
  90                         phy = <&phy3>;
  91                         phy-mode = "sgmii";
  92                 };
  93
  94                 mvsdio@d00d4000 {
  95                         pinctrl-0 = <&sdio_pins>;
  96                         pinctrl-names = "default";
  97                         status = "okay";
  98                         /* No CD or WP GPIOs */
  99                 };
 100
 101                 usb@d0050000 {
 102                         status = "okay";
 103                 };
 104
 105                 usb@d0051000 {
 106                         status = "okay";
 107                 };
 108
 109                 usb@d0052000 {
 110                         status = "okay";
 111                 };
 112
 113                 spi0: spi@d0010600 {
 114                         status = "okay";
 115
 116                         spi-flash@0 {
 117                                 #address-cells = <1>;
 118                                 #size-cells = <1>;
 119                                 compatible = "m25p64";
 120                                 reg = <0>; /* Chip select 0 */
 121                                 spi-max-frequency = <20000000>;
 122                         };
 123                 };
 124
 125                 pcie-controller {
 126                         status = "okay";
 127
 128                         /*
 129                          * All 6 slots are physically present as
 130                          * standard PCIe slots on the board.
 131                          */
 132                         pcie@1,0 {
 133                                 /* Port 0, Lane 0 */
 134                                 status = "okay";
 135                         };
 136                         pcie@2,0 {
 137                                 /* Port 0, Lane 1 */
 138                                 status = "okay";
 139                         };
 140                         pcie@3,0 {
 141                                 /* Port 0, Lane 2 */
 142                                 status = "okay";
 143                         };
 144                         pcie@4,0 {
 145                                 /* Port 0, Lane 3 */
 146                                 status = "okay";
 147                         };
 148                         pcie@9,0 {
 149                                 /* Port 2, Lane 0 */
 150                                 status = "okay";
 151                         };
 152                         pcie@10,0 {
 153                                 /* Port 3, Lane 0 */
 154                                 status = "okay";
 155                         };
 156                 };
 157         };
 158 };