2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
19 /include/ "skeleton.dtsi"
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada-370-xp";
27 compatible = "marvell,sheeva-v7";
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
38 coherency-fabric@d0020200 {
39 compatible = "marvell,coherency-fabric";
40 reg = <0xd0020200 0xb0>,
47 compatible = "simple-bus";
48 interrupt-parent = <&mpic>;
52 compatible = "snps,dw-apb-uart";
53 reg = <0xd0012000 0x100>;
60 compatible = "snps,dw-apb-uart";
61 reg = <0xd0012100 0x100>;
69 compatible = "marvell,armada-370-xp-timer";
70 reg = <0xd0020300 0x30>,
72 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
73 clocks = <&coreclk 2>;
77 compatible = "marvell,orion-sata";
78 reg = <0xd00a0000 0x2400>;
80 clocks = <&gateclk 15>, <&gateclk 30>;
81 clock-names = "0", "1";
88 compatible = "marvell,orion-mdio";
89 reg = <0xd0072004 0x4>;
93 compatible = "marvell,armada-370-neta";
94 reg = <0xd0070000 0x2500>;
96 clocks = <&gateclk 4>;
101 compatible = "marvell,armada-370-neta";
102 reg = <0xd0074000 0x2500>;
104 clocks = <&gateclk 3>;
109 compatible = "marvell,mv64xxx-i2c";
110 reg = <0xd0011000 0x20>;
111 #address-cells = <1>;
115 clocks = <&coreclk 0>;
120 compatible = "marvell,mv64xxx-i2c";
121 reg = <0xd0011100 0x20>;
122 #address-cells = <1>;
126 clocks = <&coreclk 0>;
131 compatible = "marvell,orion-rtc";
132 reg = <0xd0010300 0x20>;
137 compatible = "marvell,orion-sdio";
138 reg = <0xd00d4000 0x200>;
140 clocks = <&gateclk 17>;
145 compatible = "marvell,orion-ehci";
146 reg = <0xd0050000 0x500>;
152 compatible = "marvell,orion-ehci";
153 reg = <0xd0051000 0x500>;
159 compatible = "marvell,orion-spi";
160 reg = <0xd0010600 0x28>;
161 #address-cells = <1>;
165 clocks = <&coreclk 0>;
170 compatible = "marvell,orion-spi";
171 reg = <0xd0010680 0x28>;
172 #address-cells = <1>;
176 clocks = <&coreclk 0>;
180 devbus-bootcs@d0010400 {
181 compatible = "marvell,mvebu-devbus";
182 reg = <0xd0010400 0x8>;
183 #address-cells = <1>;
185 clocks = <&coreclk 0>;
189 devbus-cs0@d0010408 {
190 compatible = "marvell,mvebu-devbus";
191 reg = <0xd0010408 0x8>;
192 #address-cells = <1>;
194 clocks = <&coreclk 0>;
198 devbus-cs1@d0010410 {
199 compatible = "marvell,mvebu-devbus";
200 reg = <0xd0010410 0x8>;
201 #address-cells = <1>;
203 clocks = <&coreclk 0>;
207 devbus-cs2@d0010418 {
208 compatible = "marvell,mvebu-devbus";
209 reg = <0xd0010418 0x8>;
210 #address-cells = <1>;
212 clocks = <&coreclk 0>;
216 devbus-cs3@d0010420 {
217 compatible = "marvell,mvebu-devbus";
218 reg = <0xd0010420 0x8>;
219 #address-cells = <1>;
221 clocks = <&coreclk 0>;