Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/am43xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for AM43xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &scrm_clocks {
  11         sys_clkin_ck: sys_clkin_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "ti,mux-clock";
  14                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  15                 ti,bit-shift = <22>;
  16                 reg = <0x0040>;
  17         };
  18
  19         adc_tsc_fck: adc_tsc_fck {
  20                 #clock-cells = <0>;
  21                 compatible = "fixed-factor-clock";
  22                 clocks = <&sys_clkin_ck>;
  23                 clock-mult = <1>;
  24                 clock-div = <1>;
  25         };
  26
  27         dcan0_fck: dcan0_fck {
  28                 #clock-cells = <0>;
  29                 compatible = "fixed-factor-clock";
  30                 clocks = <&sys_clkin_ck>;
  31                 clock-mult = <1>;
  32                 clock-div = <1>;
  33         };
  34
  35         dcan1_fck: dcan1_fck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-factor-clock";
  38                 clocks = <&sys_clkin_ck>;
  39                 clock-mult = <1>;
  40                 clock-div = <1>;
  41         };
  42
  43         mcasp0_fck: mcasp0_fck {
  44                 #clock-cells = <0>;
  45                 compatible = "fixed-factor-clock";
  46                 clocks = <&sys_clkin_ck>;
  47                 clock-mult = <1>;
  48                 clock-div = <1>;
  49         };
  50
  51         mcasp1_fck: mcasp1_fck {
  52                 #clock-cells = <0>;
  53                 compatible = "fixed-factor-clock";
  54                 clocks = <&sys_clkin_ck>;
  55                 clock-mult = <1>;
  56                 clock-div = <1>;
  57         };
  58
  59         smartreflex0_fck: smartreflex0_fck {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-factor-clock";
  62                 clocks = <&sys_clkin_ck>;
  63                 clock-mult = <1>;
  64                 clock-div = <1>;
  65         };
  66
  67         smartreflex1_fck: smartreflex1_fck {
  68                 #clock-cells = <0>;
  69                 compatible = "fixed-factor-clock";
  70                 clocks = <&sys_clkin_ck>;
  71                 clock-mult = <1>;
  72                 clock-div = <1>;
  73         };
  74
  75         sha0_fck: sha0_fck {
  76                 #clock-cells = <0>;
  77                 compatible = "fixed-factor-clock";
  78                 clocks = <&sys_clkin_ck>;
  79                 clock-mult = <1>;
  80                 clock-div = <1>;
  81         };
  82
  83         aes0_fck: aes0_fck {
  84                 #clock-cells = <0>;
  85                 compatible = "fixed-factor-clock";
  86                 clocks = <&sys_clkin_ck>;
  87                 clock-mult = <1>;
  88                 clock-div = <1>;
  89         };
  90 };
  91 &prcm_clocks {
  92         clk_32768_ck: clk_32768_ck {
  93                 #clock-cells = <0>;
  94                 compatible = "fixed-clock";
  95                 clock-frequency = <32768>;
  96         };
  97
  98         clk_rc32k_ck: clk_rc32k_ck {
  99                 #clock-cells = <0>;
 100                 compatible = "fixed-clock";
 101                 clock-frequency = <32768>;
 102         };
 103
 104         virt_19200000_ck: virt_19200000_ck {
 105                 #clock-cells = <0>;
 106                 compatible = "fixed-clock";
 107                 clock-frequency = <19200000>;
 108         };
 109
 110         virt_24000000_ck: virt_24000000_ck {
 111                 #clock-cells = <0>;
 112                 compatible = "fixed-clock";
 113                 clock-frequency = <24000000>;
 114         };
 115
 116         virt_25000000_ck: virt_25000000_ck {
 117                 #clock-cells = <0>;
 118                 compatible = "fixed-clock";
 119                 clock-frequency = <25000000>;
 120         };
 121
 122         virt_26000000_ck: virt_26000000_ck {
 123                 #clock-cells = <0>;
 124                 compatible = "fixed-clock";
 125                 clock-frequency = <26000000>;
 126         };
 127
 128         tclkin_ck: tclkin_ck {
 129                 #clock-cells = <0>;
 130                 compatible = "fixed-clock";
 131                 clock-frequency = <26000000>;
 132         };
 133
 134         dpll_core_ck: dpll_core_ck {
 135                 #clock-cells = <0>;
 136                 compatible = "ti,am3-dpll-core-clock";
 137                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 138                 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
 139         };
 140
 141         dpll_core_x2_ck: dpll_core_x2_ck {
 142                 #clock-cells = <0>;
 143                 compatible = "ti,am3-dpll-x2-clock";
 144                 clocks = <&dpll_core_ck>;
 145         };
 146
 147         dpll_core_m4_ck: dpll_core_m4_ck {
 148                 #clock-cells = <0>;
 149                 compatible = "ti,divider-clock";
 150                 clocks = <&dpll_core_x2_ck>;
 151                 ti,max-div = <31>;
 152                 ti,autoidle-shift = <8>;
 153                 reg = <0x2d38>;
 154                 ti,index-starts-at-one;
 155                 ti,invert-autoidle-bit;
 156         };
 157
 158         dpll_core_m5_ck: dpll_core_m5_ck {
 159                 #clock-cells = <0>;
 160                 compatible = "ti,divider-clock";
 161                 clocks = <&dpll_core_x2_ck>;
 162                 ti,max-div = <31>;
 163                 ti,autoidle-shift = <8>;
 164                 reg = <0x2d3c>;
 165                 ti,index-starts-at-one;
 166                 ti,invert-autoidle-bit;
 167         };
 168
 169         dpll_core_m6_ck: dpll_core_m6_ck {
 170                 #clock-cells = <0>;
 171                 compatible = "ti,divider-clock";
 172                 clocks = <&dpll_core_x2_ck>;
 173                 ti,max-div = <31>;
 174                 ti,autoidle-shift = <8>;
 175                 reg = <0x2d40>;
 176                 ti,index-starts-at-one;
 177                 ti,invert-autoidle-bit;
 178         };
 179
 180         dpll_mpu_ck: dpll_mpu_ck {
 181                 #clock-cells = <0>;
 182                 compatible = "ti,am3-dpll-clock";
 183                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 184                 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
 185         };
 186
 187         dpll_mpu_m2_ck: dpll_mpu_m2_ck {
 188                 #clock-cells = <0>;
 189                 compatible = "ti,divider-clock";
 190                 clocks = <&dpll_mpu_ck>;
 191                 ti,max-div = <31>;
 192                 ti,autoidle-shift = <8>;
 193                 reg = <0x2d70>;
 194                 ti,index-starts-at-one;
 195                 ti,invert-autoidle-bit;
 196         };
 197
 198         dpll_ddr_ck: dpll_ddr_ck {
 199                 #clock-cells = <0>;
 200                 compatible = "ti,am3-dpll-clock";
 201                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 202                 reg = <0x2da0>, <0x2da4>, <0x2dac>;
 203         };
 204
 205         dpll_ddr_m2_ck: dpll_ddr_m2_ck {
 206                 #clock-cells = <0>;
 207                 compatible = "ti,divider-clock";
 208                 clocks = <&dpll_ddr_ck>;
 209                 ti,max-div = <31>;
 210                 ti,autoidle-shift = <8>;
 211                 reg = <0x2db0>;
 212                 ti,index-starts-at-one;
 213                 ti,invert-autoidle-bit;
 214         };
 215
 216         dpll_disp_ck: dpll_disp_ck {
 217                 #clock-cells = <0>;
 218                 compatible = "ti,am3-dpll-clock";
 219                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 220                 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
 221         };
 222
 223         dpll_disp_m2_ck: dpll_disp_m2_ck {
 224                 #clock-cells = <0>;
 225                 compatible = "ti,divider-clock";
 226                 clocks = <&dpll_disp_ck>;
 227                 ti,max-div = <31>;
 228                 ti,autoidle-shift = <8>;
 229                 reg = <0x2e30>;
 230                 ti,index-starts-at-one;
 231                 ti,invert-autoidle-bit;
 232         };
 233
 234         dpll_per_ck: dpll_per_ck {
 235                 #clock-cells = <0>;
 236                 compatible = "ti,am3-dpll-j-type-clock";
 237                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 238                 reg = <0x2de0>, <0x2de4>, <0x2dec>;
 239         };
 240
 241         dpll_per_m2_ck: dpll_per_m2_ck {
 242                 #clock-cells = <0>;
 243                 compatible = "ti,divider-clock";
 244                 clocks = <&dpll_per_ck>;
 245                 ti,max-div = <127>;
 246                 ti,autoidle-shift = <8>;
 247                 reg = <0x2df0>;
 248                 ti,index-starts-at-one;
 249                 ti,invert-autoidle-bit;
 250         };
 251
 252         dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
 253                 #clock-cells = <0>;
 254                 compatible = "fixed-factor-clock";
 255                 clocks = <&dpll_per_m2_ck>;
 256                 clock-mult = <1>;
 257                 clock-div = <4>;
 258         };
 259
 260         dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
 261                 #clock-cells = <0>;
 262                 compatible = "fixed-factor-clock";
 263                 clocks = <&dpll_per_m2_ck>;
 264                 clock-mult = <1>;
 265                 clock-div = <4>;
 266         };
 267
 268         clk_24mhz: clk_24mhz {
 269                 #clock-cells = <0>;
 270                 compatible = "fixed-factor-clock";
 271                 clocks = <&dpll_per_m2_ck>;
 272                 clock-mult = <1>;
 273                 clock-div = <8>;
 274         };
 275
 276         clkdiv32k_ck: clkdiv32k_ck {
 277                 #clock-cells = <0>;
 278                 compatible = "fixed-factor-clock";
 279                 clocks = <&clk_24mhz>;
 280                 clock-mult = <1>;
 281                 clock-div = <732>;
 282         };
 283
 284         clkdiv32k_ick: clkdiv32k_ick {
 285                 #clock-cells = <0>;
 286                 compatible = "ti,gate-clock";
 287                 clocks = <&clkdiv32k_ck>;
 288                 ti,bit-shift = <8>;
 289                 reg = <0x2a38>;
 290         };
 291
 292         sysclk_div: sysclk_div {
 293                 #clock-cells = <0>;
 294                 compatible = "fixed-factor-clock";
 295                 clocks = <&dpll_core_m4_ck>;
 296                 clock-mult = <1>;
 297                 clock-div = <1>;
 298         };
 299
 300         pruss_ocp_gclk: pruss_ocp_gclk {
 301                 #clock-cells = <0>;
 302                 compatible = "ti,mux-clock";
 303                 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
 304                 reg = <0x4248>;
 305         };
 306
 307         clk_32k_tpm_ck: clk_32k_tpm_ck {
 308                 #clock-cells = <0>;
 309                 compatible = "fixed-clock";
 310                 clock-frequency = <32768>;
 311         };
 312
 313         timer1_fck: timer1_fck {
 314                 #clock-cells = <0>;
 315                 compatible = "ti,mux-clock";
 316                 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 317                 reg = <0x4200>;
 318         };
 319
 320         timer2_fck: timer2_fck {
 321                 #clock-cells = <0>;
 322                 compatible = "ti,mux-clock";
 323                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 324                 reg = <0x4204>;
 325         };
 326
 327         timer3_fck: timer3_fck {
 328                 #clock-cells = <0>;
 329                 compatible = "ti,mux-clock";
 330                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 331                 reg = <0x4208>;
 332         };
 333
 334         timer4_fck: timer4_fck {
 335                 #clock-cells = <0>;
 336                 compatible = "ti,mux-clock";
 337                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 338                 reg = <0x420c>;
 339         };
 340
 341         timer5_fck: timer5_fck {
 342                 #clock-cells = <0>;
 343                 compatible = "ti,mux-clock";
 344                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 345                 reg = <0x4210>;
 346         };
 347
 348         timer6_fck: timer6_fck {
 349                 #clock-cells = <0>;
 350                 compatible = "ti,mux-clock";
 351                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 352                 reg = <0x4214>;
 353         };
 354
 355         timer7_fck: timer7_fck {
 356                 #clock-cells = <0>;
 357                 compatible = "ti,mux-clock";
 358                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 359                 reg = <0x4218>;
 360         };
 361
 362         wdt1_fck: wdt1_fck {
 363                 #clock-cells = <0>;
 364                 compatible = "ti,mux-clock";
 365                 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
 366                 reg = <0x422c>;
 367         };
 368
 369         l3_gclk: l3_gclk {
 370                 #clock-cells = <0>;
 371                 compatible = "fixed-factor-clock";
 372                 clocks = <&dpll_core_m4_ck>;
 373                 clock-mult = <1>;
 374                 clock-div = <1>;
 375         };
 376
 377         dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
 378                 #clock-cells = <0>;
 379                 compatible = "fixed-factor-clock";
 380                 clocks = <&sysclk_div>;
 381                 clock-mult = <1>;
 382                 clock-div = <2>;
 383         };
 384
 385         l4hs_gclk: l4hs_gclk {
 386                 #clock-cells = <0>;
 387                 compatible = "fixed-factor-clock";
 388                 clocks = <&dpll_core_m4_ck>;
 389                 clock-mult = <1>;
 390                 clock-div = <1>;
 391         };
 392
 393         l3s_gclk: l3s_gclk {
 394                 #clock-cells = <0>;
 395                 compatible = "fixed-factor-clock";
 396                 clocks = <&dpll_core_m4_div2_ck>;
 397                 clock-mult = <1>;
 398                 clock-div = <1>;
 399         };
 400
 401         l4ls_gclk: l4ls_gclk {
 402                 #clock-cells = <0>;
 403                 compatible = "fixed-factor-clock";
 404                 clocks = <&dpll_core_m4_div2_ck>;
 405                 clock-mult = <1>;
 406                 clock-div = <1>;
 407         };
 408
 409         cpsw_125mhz_gclk: cpsw_125mhz_gclk {
 410                 #clock-cells = <0>;
 411                 compatible = "fixed-factor-clock";
 412                 clocks = <&dpll_core_m5_ck>;
 413                 clock-mult = <1>;
 414                 clock-div = <2>;
 415         };
 416
 417         cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
 418                 #clock-cells = <0>;
 419                 compatible = "ti,mux-clock";
 420                 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
 421                 reg = <0x4238>;
 422         };
 423
 424         clk_32k_mosc_ck: clk_32k_mosc_ck {
 425                 #clock-cells = <0>;
 426                 compatible = "fixed-clock";
 427                 clock-frequency = <32768>;
 428         };
 429
 430         gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
 431                 #clock-cells = <0>;
 432                 compatible = "ti,mux-clock";
 433                 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
 434                 reg = <0x4240>;
 435         };
 436
 437         gpio0_dbclk: gpio0_dbclk {
 438                 #clock-cells = <0>;
 439                 compatible = "ti,gate-clock";
 440                 clocks = <&gpio0_dbclk_mux_ck>;
 441                 ti,bit-shift = <8>;
 442                 reg = <0x2b68>;
 443         };
 444
 445         gpio1_dbclk: gpio1_dbclk {
 446                 #clock-cells = <0>;
 447                 compatible = "ti,gate-clock";
 448                 clocks = <&clkdiv32k_ick>;
 449                 ti,bit-shift = <8>;
 450                 reg = <0x8c78>;
 451         };
 452
 453         gpio2_dbclk: gpio2_dbclk {
 454                 #clock-cells = <0>;
 455                 compatible = "ti,gate-clock";
 456                 clocks = <&clkdiv32k_ick>;
 457                 ti,bit-shift = <8>;
 458                 reg = <0x8c80>;
 459         };
 460
 461         gpio3_dbclk: gpio3_dbclk {
 462                 #clock-cells = <0>;
 463                 compatible = "ti,gate-clock";
 464                 clocks = <&clkdiv32k_ick>;
 465                 ti,bit-shift = <8>;
 466                 reg = <0x8c88>;
 467         };
 468
 469         gpio4_dbclk: gpio4_dbclk {
 470                 #clock-cells = <0>;
 471                 compatible = "ti,gate-clock";
 472                 clocks = <&clkdiv32k_ick>;
 473                 ti,bit-shift = <8>;
 474                 reg = <0x8c90>;
 475         };
 476
 477         gpio5_dbclk: gpio5_dbclk {
 478                 #clock-cells = <0>;
 479                 compatible = "ti,gate-clock";
 480                 clocks = <&clkdiv32k_ick>;
 481                 ti,bit-shift = <8>;
 482                 reg = <0x8c98>;
 483         };
 484
 485         mmc_clk: mmc_clk {
 486                 #clock-cells = <0>;
 487                 compatible = "fixed-factor-clock";
 488                 clocks = <&dpll_per_m2_ck>;
 489                 clock-mult = <1>;
 490                 clock-div = <2>;
 491         };
 492
 493         gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
 494                 #clock-cells = <0>;
 495                 compatible = "ti,mux-clock";
 496                 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
 497                 ti,bit-shift = <1>;
 498                 reg = <0x423c>;
 499         };
 500
 501         gfx_fck_div_ck: gfx_fck_div_ck {
 502                 #clock-cells = <0>;
 503                 compatible = "ti,divider-clock";
 504                 clocks = <&gfx_fclk_clksel_ck>;
 505                 reg = <0x423c>;
 506                 ti,max-div = <2>;
 507         };
 508
 509         disp_clk: disp_clk {
 510                 #clock-cells = <0>;
 511                 compatible = "ti,mux-clock";
 512                 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
 513                 reg = <0x4244>;
 514         };
 515
 516         dpll_extdev_ck: dpll_extdev_ck {
 517                 #clock-cells = <0>;
 518                 compatible = "ti,am3-dpll-clock";
 519                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 520                 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
 521         };
 522
 523         dpll_extdev_m2_ck: dpll_extdev_m2_ck {
 524                 #clock-cells = <0>;
 525                 compatible = "ti,divider-clock";
 526                 clocks = <&dpll_extdev_ck>;
 527                 ti,max-div = <127>;
 528                 ti,autoidle-shift = <8>;
 529                 reg = <0x2e70>;
 530                 ti,index-starts-at-one;
 531                 ti,invert-autoidle-bit;
 532         };
 533
 534         mux_synctimer32k_ck: mux_synctimer32k_ck {
 535                 #clock-cells = <0>;
 536                 compatible = "ti,mux-clock";
 537                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
 538                 reg = <0x4230>;
 539         };
 540
 541         synctimer_32kclk: synctimer_32kclk {
 542                 #clock-cells = <0>;
 543                 compatible = "ti,gate-clock";
 544                 clocks = <&mux_synctimer32k_ck>;
 545                 ti,bit-shift = <8>;
 546                 reg = <0x2a30>;
 547         };
 548
 549         timer8_fck: timer8_fck {
 550                 #clock-cells = <0>;
 551                 compatible = "ti,mux-clock";
 552                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 553                 reg = <0x421c>;
 554         };
 555
 556         timer9_fck: timer9_fck {
 557                 #clock-cells = <0>;
 558                 compatible = "ti,mux-clock";
 559                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 560                 reg = <0x4220>;
 561         };
 562
 563         timer10_fck: timer10_fck {
 564                 #clock-cells = <0>;
 565                 compatible = "ti,mux-clock";
 566                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 567                 reg = <0x4224>;
 568         };
 569
 570         timer11_fck: timer11_fck {
 571                 #clock-cells = <0>;
 572                 compatible = "ti,mux-clock";
 573                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 574                 reg = <0x4228>;
 575         };
 576
 577         cpsw_50m_clkdiv: cpsw_50m_clkdiv {
 578                 #clock-cells = <0>;
 579                 compatible = "fixed-factor-clock";
 580                 clocks = <&dpll_core_m5_ck>;
 581                 clock-mult = <1>;
 582                 clock-div = <1>;
 583         };
 584
 585         cpsw_5m_clkdiv: cpsw_5m_clkdiv {
 586                 #clock-cells = <0>;
 587                 compatible = "fixed-factor-clock";
 588                 clocks = <&cpsw_50m_clkdiv>;
 589                 clock-mult = <1>;
 590                 clock-div = <10>;
 591         };
 592
 593         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 594                 #clock-cells = <0>;
 595                 compatible = "ti,am3-dpll-x2-clock";
 596                 clocks = <&dpll_ddr_ck>;
 597         };
 598
 599         dpll_ddr_m4_ck: dpll_ddr_m4_ck {
 600                 #clock-cells = <0>;
 601                 compatible = "ti,divider-clock";
 602                 clocks = <&dpll_ddr_x2_ck>;
 603                 ti,max-div = <31>;
 604                 ti,autoidle-shift = <8>;
 605                 reg = <0x2db8>;
 606                 ti,index-starts-at-one;
 607                 ti,invert-autoidle-bit;
 608         };
 609
 610         dpll_per_clkdcoldo: dpll_per_clkdcoldo {
 611                 #clock-cells = <0>;
 612                 compatible = "fixed-factor-clock";
 613                 clocks = <&dpll_per_ck>;
 614                 clock-mult = <1>;
 615                 clock-div = <1>;
 616         };
 617
 618         dll_aging_clk_div: dll_aging_clk_div {
 619                 #clock-cells = <0>;
 620                 compatible = "ti,divider-clock";
 621                 clocks = <&sys_clkin_ck>;
 622                 reg = <0x4250>;
 623                 ti,dividers = <8>, <16>, <32>;
 624         };
 625
 626         div_core_25m_ck: div_core_25m_ck {
 627                 #clock-cells = <0>;
 628                 compatible = "fixed-factor-clock";
 629                 clocks = <&sysclk_div>;
 630                 clock-mult = <1>;
 631                 clock-div = <8>;
 632         };
 633
 634         func_12m_clk: func_12m_clk {
 635                 #clock-cells = <0>;
 636                 compatible = "fixed-factor-clock";
 637                 clocks = <&dpll_per_m2_ck>;
 638                 clock-mult = <1>;
 639                 clock-div = <16>;
 640         };
 641
 642         vtp_clk_div: vtp_clk_div {
 643                 #clock-cells = <0>;
 644                 compatible = "fixed-factor-clock";
 645                 clocks = <&sys_clkin_ck>;
 646                 clock-mult = <1>;
 647                 clock-div = <2>;
 648         };
 649
 650         usbphy_32khz_clkmux: usbphy_32khz_clkmux {
 651                 #clock-cells = <0>;
 652                 compatible = "ti,mux-clock";
 653                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 654                 reg = <0x4260>;
 655         };
 656 };