4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
256 select ARCH_HAS_CPUFREQ
258 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_CLOCK
264 select PLAT_VERSATILE_FPGA_IRQ
265 select NEED_MACH_IO_H
266 select NEED_MACH_MEMORY_H
268 select MULTI_IRQ_HANDLER
270 Support for ARM's Integrator platform.
273 bool "ARM Ltd. RealView family"
276 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLOCK
282 select PLAT_VERSATILE_CLCD
283 select ARM_TIMER_SP804
284 select GPIO_PL061 if GPIOLIB
285 select NEED_MACH_MEMORY_H
287 This enables support for ARM Ltd RealView boards.
289 config ARCH_VERSATILE
290 bool "ARM Ltd. Versatile family"
294 select HAVE_MACH_CLKDEV
296 select GENERIC_CLOCKEVENTS
297 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select NEED_MACH_IO_H if PCI
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
301 select PLAT_VERSATILE_CLCD
302 select PLAT_VERSATILE_FPGA_IRQ
303 select ARM_TIMER_SP804
305 This enables support for ARM Ltd Versatile board.
308 bool "ARM Ltd. Versatile Express family"
309 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_TIMER_SP804
314 select GENERIC_CLOCKEVENTS
316 select HAVE_PATA_PLATFORM
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select REGULATOR_FIXED_VOLTAGE if REGULATOR
323 This enables support for the ARM Ltd Versatile Express boards.
327 select ARCH_REQUIRE_GPIOLIB
331 select NEED_MACH_IO_H if PCCARD
333 This enables support for systems based on Atmel
334 AT91RM9200 and AT91SAM9* processors.
337 bool "Broadcom BCMRING"
341 select ARM_TIMER_SP804
343 select GENERIC_CLOCKEVENTS
344 select ARCH_WANT_OPTIONAL_GPIOLIB
346 Support for Broadcom's BCMRing platform.
349 bool "Calxeda Highbank-based"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
353 select ARM_TIMER_SP804
357 select GENERIC_CLOCKEVENTS
363 Support for the Calxeda Highbank SoC based boards.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
368 select ARCH_USES_GETTIMEOFFSET
369 select NEED_MACH_MEMORY_H
371 Support for Cirrus Logic 711x/721x/731x based boards.
374 bool "Cavium Networks CNS3XXX family"
376 select GENERIC_CLOCKEVENTS
378 select MIGHT_HAVE_CACHE_L2X0
379 select MIGHT_HAVE_PCI
380 select PCI_DOMAINS if PCI
382 Support for Cavium Networks CNS3XXX platform.
385 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
390 Support for the Cortina Systems Gemini family SoCs
393 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
396 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
405 Support for CSR SiRFSoC ARM Cortex A9 Platform
412 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
427 select ARCH_REQUIRE_GPIOLIB
428 select ARCH_HAS_HOLES_MEMORYMODEL
429 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Freescale MXC/iMX-based"
448 select GENERIC_CLOCKEVENTS
449 select ARCH_REQUIRE_GPIOLIB
452 select GENERIC_IRQ_CHIP
453 select MULTI_IRQ_HANDLER
455 Support for Freescale MXC/iMX-based family of processors
458 bool "Freescale MXS-based"
459 select GENERIC_CLOCKEVENTS
460 select ARCH_REQUIRE_GPIOLIB
464 select HAVE_CLK_PREPARE
468 Support for Freescale MXS-based family of processors
471 bool "Hilscher NetX based"
475 select GENERIC_CLOCKEVENTS
477 This enables support for systems based on the Hilscher NetX Soc
480 bool "Hynix HMS720x-based"
483 select ARCH_USES_GETTIMEOFFSET
485 This enables support for systems based on the Hynix HMS720x
493 select ARCH_SUPPORTS_MSI
495 select NEED_MACH_IO_H
496 select NEED_MACH_MEMORY_H
497 select NEED_RET_TO_USER
499 Support for Intel's IOP13XX (XScale) family of processors.
505 select NEED_MACH_IO_H
506 select NEED_RET_TO_USER
509 select ARCH_REQUIRE_GPIOLIB
511 Support for Intel's 80219 and IOP32X (XScale) family of
518 select NEED_MACH_IO_H
519 select NEED_RET_TO_USER
522 select ARCH_REQUIRE_GPIOLIB
524 Support for Intel's IOP33X (XScale) family of processors.
529 select ARCH_HAS_DMA_SET_COHERENT_MASK
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
535 select NEED_MACH_IO_H
536 select DMABOUNCE if PCI
538 Support for Intel's IXP4XX (XScale) family of processors.
544 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select NEED_MACH_IO_H
549 Support for the Marvell Dove SoC 88AP510
552 bool "Marvell Kirkwood"
555 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
557 select NEED_MACH_IO_H
560 Support for the following Marvell Kirkwood series SoCs:
561 88F6180, 88F6192 and 88F6281.
567 select ARCH_REQUIRE_GPIOLIB
570 select USB_ARCH_HAS_OHCI
572 select GENERIC_CLOCKEVENTS
575 Support for the NXP LPC32XX family of processors
578 bool "Marvell MV78xx0"
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select NEED_MACH_IO_H
586 Support for the following Marvell MV78xx0 series SoCs:
594 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
596 select NEED_MACH_IO_H
599 Support for the following Marvell Orion 5x series SoCs:
600 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
601 Orion-2 (5281), Orion-1-90 (6183).
604 bool "Marvell PXA168/910/MMP2"
606 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
613 select GENERIC_ALLOCATOR
615 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
618 bool "Micrel/Kendin KS8695"
620 select ARCH_REQUIRE_GPIOLIB
621 select ARCH_USES_GETTIMEOFFSET
622 select NEED_MACH_MEMORY_H
624 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
625 System-on-Chip devices.
628 bool "Nuvoton W90X900 CPU"
630 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
635 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
636 At present, the w90x900 has been renamed nuc900, regarding
637 the ARM series product line, you can login the following
638 link address to know more.
640 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
641 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
647 select GENERIC_CLOCKEVENTS
651 select MIGHT_HAVE_CACHE_L2X0
652 select NEED_MACH_IO_H if PCI
653 select ARCH_HAS_CPUFREQ
655 This enables support for NVIDIA Tegra based systems (Tegra APX,
656 Tegra 6xx and Tegra 2 series).
658 config ARCH_PICOXCELL
659 bool "Picochip picoXcell"
660 select ARCH_REQUIRE_GPIOLIB
661 select ARM_PATCH_PHYS_VIRT
665 select GENERIC_CLOCKEVENTS
672 This enables support for systems based on the Picochip picoXcell
673 family of Femtocell devices. The picoxcell support requires device tree
677 bool "Philips Nexperia PNX4008 Mobile"
680 select ARCH_USES_GETTIMEOFFSET
682 This enables support for Philips PNX4008 mobile platform.
685 bool "PXA2xx/PXA3xx-based"
688 select ARCH_HAS_CPUFREQ
691 select ARCH_REQUIRE_GPIOLIB
692 select GENERIC_CLOCKEVENTS
697 select MULTI_IRQ_HANDLER
698 select ARM_CPU_SUSPEND if PM
701 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
706 select GENERIC_CLOCKEVENTS
707 select ARCH_REQUIRE_GPIOLIB
710 Support for Qualcomm MSM/QSD based systems. This runs on the
711 apps processor of the MSM/QSD and depends on a shared memory
712 interface to the modem processor which runs the baseband
713 stack and controls some vital subsystems
714 (clock and power control, etc).
717 bool "Renesas SH-Mobile / R-Mobile"
720 select HAVE_MACH_CLKDEV
722 select GENERIC_CLOCKEVENTS
723 select MIGHT_HAVE_CACHE_L2X0
726 select MULTI_IRQ_HANDLER
727 select PM_GENERIC_DOMAINS if PM
728 select NEED_MACH_MEMORY_H
730 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
736 select ARCH_MAY_HAVE_PC_FDC
737 select HAVE_PATA_PLATFORM
740 select ARCH_SPARSEMEM_ENABLE
741 select ARCH_USES_GETTIMEOFFSET
743 select NEED_MACH_IO_H
744 select NEED_MACH_MEMORY_H
746 On the Acorn Risc-PC, Linux can support the internal IDE disk and
747 CD-ROM interface, serial and parallel port, and the floppy drive.
754 select ARCH_SPARSEMEM_ENABLE
756 select ARCH_HAS_CPUFREQ
758 select GENERIC_CLOCKEVENTS
760 select ARCH_REQUIRE_GPIOLIB
762 select NEED_MACH_MEMORY_H
765 Support for StrongARM 11x0 based boards.
768 bool "Samsung S3C24XX SoCs"
770 select ARCH_HAS_CPUFREQ
773 select ARCH_USES_GETTIMEOFFSET
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C_RTC if RTC_CLASS
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select NEED_MACH_IO_H
779 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
780 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
781 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
782 Samsung SMDK2410 development board (and derivatives).
785 bool "Samsung S3C64XX"
793 select ARCH_USES_GETTIMEOFFSET
794 select ARCH_HAS_CPUFREQ
795 select ARCH_REQUIRE_GPIOLIB
796 select SAMSUNG_CLKSRC
797 select SAMSUNG_IRQ_VIC_TIMER
798 select S3C_GPIO_TRACK
800 select USB_ARCH_HAS_OHCI
801 select SAMSUNG_GPIOLIB_4BIT
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 Samsung S3C64XX series based systems
808 bool "Samsung S5P6440 S5P6450"
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select GENERIC_CLOCKEVENTS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
819 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
823 bool "Samsung S5PC100"
828 select ARCH_USES_GETTIMEOFFSET
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C_RTC if RTC_CLASS
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
833 Samsung S5PC100 series based systems
836 bool "Samsung S5PV210/S5PC110"
838 select ARCH_SPARSEMEM_ENABLE
839 select ARCH_HAS_HOLES_MEMORYMODEL
844 select ARCH_HAS_CPUFREQ
845 select GENERIC_CLOCKEVENTS
846 select HAVE_S3C2410_I2C if I2C
847 select HAVE_S3C_RTC if RTC_CLASS
848 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 select NEED_MACH_MEMORY_H
851 Samsung S5PV210/S5PC110 series based systems
854 bool "SAMSUNG EXYNOS"
856 select ARCH_SPARSEMEM_ENABLE
857 select ARCH_HAS_HOLES_MEMORYMODEL
861 select ARCH_HAS_CPUFREQ
862 select GENERIC_CLOCKEVENTS
863 select HAVE_S3C_RTC if RTC_CLASS
864 select HAVE_S3C2410_I2C if I2C
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
866 select NEED_MACH_MEMORY_H
868 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
877 select ARCH_USES_GETTIMEOFFSET
878 select NEED_MACH_MEMORY_H
879 select NEED_MACH_IO_H
881 Support for the StrongARM based Digital DNARD machine, also known
882 as "Shark" (<http://www.shark-linux.de/shark.html>).
885 bool "ST-Ericsson U300 Series"
891 select ARM_PATCH_PHYS_VIRT
893 select GENERIC_CLOCKEVENTS
895 select HAVE_MACH_CLKDEV
897 select ARCH_REQUIRE_GPIOLIB
899 Support for ST-Ericsson U300 series mobile platforms.
902 bool "ST-Ericsson U8500 Series"
906 select GENERIC_CLOCKEVENTS
908 select ARCH_REQUIRE_GPIOLIB
909 select ARCH_HAS_CPUFREQ
911 select MIGHT_HAVE_CACHE_L2X0
913 Support for ST-Ericsson's Ux500 architecture
916 bool "STMicroelectronics Nomadik"
921 select GENERIC_CLOCKEVENTS
923 select MIGHT_HAVE_CACHE_L2X0
924 select ARCH_REQUIRE_GPIOLIB
926 Support for the Nomadik platform by ST-Ericsson
930 select GENERIC_CLOCKEVENTS
931 select ARCH_REQUIRE_GPIOLIB
935 select GENERIC_ALLOCATOR
936 select GENERIC_IRQ_CHIP
937 select ARCH_HAS_HOLES_MEMORYMODEL
939 Support for TI's DaVinci platform.
944 select ARCH_REQUIRE_GPIOLIB
945 select ARCH_HAS_CPUFREQ
947 select GENERIC_CLOCKEVENTS
948 select ARCH_HAS_HOLES_MEMORYMODEL
950 Support for TI's OMAP platform (OMAP1/2/3/4).
955 select ARCH_REQUIRE_GPIOLIB
959 select GENERIC_CLOCKEVENTS
962 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
965 bool "VIA/WonderMedia 85xx"
968 select ARCH_HAS_CPUFREQ
969 select GENERIC_CLOCKEVENTS
970 select ARCH_REQUIRE_GPIOLIB
973 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
976 bool "Xilinx Zynq ARM Cortex A9 Platform"
978 select GENERIC_CLOCKEVENTS
983 select MIGHT_HAVE_CACHE_L2X0
986 Support for Xilinx Zynq ARM Cortex A9 Platform
990 # This is sorted alphabetically by mach-* pathname. However, plat-*
991 # Kconfigs may be included either alphabetically (according to the
992 # plat- suffix) or along side the corresponding mach-* source.
994 source "arch/arm/mach-at91/Kconfig"
996 source "arch/arm/mach-bcmring/Kconfig"
998 source "arch/arm/mach-clps711x/Kconfig"
1000 source "arch/arm/mach-cns3xxx/Kconfig"
1002 source "arch/arm/mach-davinci/Kconfig"
1004 source "arch/arm/mach-dove/Kconfig"
1006 source "arch/arm/mach-ep93xx/Kconfig"
1008 source "arch/arm/mach-footbridge/Kconfig"
1010 source "arch/arm/mach-gemini/Kconfig"
1012 source "arch/arm/mach-h720x/Kconfig"
1014 source "arch/arm/mach-integrator/Kconfig"
1016 source "arch/arm/mach-iop32x/Kconfig"
1018 source "arch/arm/mach-iop33x/Kconfig"
1020 source "arch/arm/mach-iop13xx/Kconfig"
1022 source "arch/arm/mach-ixp4xx/Kconfig"
1024 source "arch/arm/mach-kirkwood/Kconfig"
1026 source "arch/arm/mach-ks8695/Kconfig"
1028 source "arch/arm/mach-msm/Kconfig"
1030 source "arch/arm/mach-mv78xx0/Kconfig"
1032 source "arch/arm/plat-mxc/Kconfig"
1034 source "arch/arm/mach-mxs/Kconfig"
1036 source "arch/arm/mach-netx/Kconfig"
1038 source "arch/arm/mach-nomadik/Kconfig"
1039 source "arch/arm/plat-nomadik/Kconfig"
1041 source "arch/arm/plat-omap/Kconfig"
1043 source "arch/arm/mach-omap1/Kconfig"
1045 source "arch/arm/mach-omap2/Kconfig"
1047 source "arch/arm/mach-orion5x/Kconfig"
1049 source "arch/arm/mach-pxa/Kconfig"
1050 source "arch/arm/plat-pxa/Kconfig"
1052 source "arch/arm/mach-mmp/Kconfig"
1054 source "arch/arm/mach-realview/Kconfig"
1056 source "arch/arm/mach-sa1100/Kconfig"
1058 source "arch/arm/plat-samsung/Kconfig"
1059 source "arch/arm/plat-s3c24xx/Kconfig"
1061 source "arch/arm/plat-spear/Kconfig"
1063 source "arch/arm/mach-s3c24xx/Kconfig"
1065 source "arch/arm/mach-s3c2412/Kconfig"
1066 source "arch/arm/mach-s3c2440/Kconfig"
1070 source "arch/arm/mach-s3c64xx/Kconfig"
1073 source "arch/arm/mach-s5p64x0/Kconfig"
1075 source "arch/arm/mach-s5pc100/Kconfig"
1077 source "arch/arm/mach-s5pv210/Kconfig"
1079 source "arch/arm/mach-exynos/Kconfig"
1081 source "arch/arm/mach-shmobile/Kconfig"
1083 source "arch/arm/mach-tegra/Kconfig"
1085 source "arch/arm/mach-u300/Kconfig"
1087 source "arch/arm/mach-ux500/Kconfig"
1089 source "arch/arm/mach-versatile/Kconfig"
1091 source "arch/arm/mach-vexpress/Kconfig"
1092 source "arch/arm/plat-versatile/Kconfig"
1094 source "arch/arm/mach-vt8500/Kconfig"
1096 source "arch/arm/mach-w90x900/Kconfig"
1098 # Definitions to make life easier
1104 select GENERIC_CLOCKEVENTS
1109 select GENERIC_IRQ_CHIP
1115 config PLAT_VERSATILE
1118 config ARM_TIMER_SP804
1121 select HAVE_SCHED_CLOCK
1123 source arch/arm/mm/Kconfig
1127 default 16 if ARCH_EP93XX
1131 bool "Enable iWMMXt support"
1132 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1133 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1135 Enable support for iWMMXt context switching at run time if
1136 running on a CPU that supports it.
1140 depends on CPU_XSCALE
1144 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1145 (!ARCH_OMAP3 || OMAP3_EMU)
1149 config MULTI_IRQ_HANDLER
1152 Allow each machine to specify it's own IRQ handler at run time.
1155 source "arch/arm/Kconfig-nommu"
1158 config ARM_ERRATA_326103
1159 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1162 Executing a SWP instruction to read-only memory does not set bit 11
1163 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1164 treat the access as a read, preventing a COW from occurring and
1165 causing the faulting task to livelock.
1167 config ARM_ERRATA_411920
1168 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1169 depends on CPU_V6 || CPU_V6K
1171 Invalidation of the Instruction Cache operation can
1172 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1173 It does not affect the MPCore. This option enables the ARM Ltd.
1174 recommended workaround.
1176 config ARM_ERRATA_430973
1177 bool "ARM errata: Stale prediction on replaced interworking branch"
1180 This option enables the workaround for the 430973 Cortex-A8
1181 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1182 interworking branch is replaced with another code sequence at the
1183 same virtual address, whether due to self-modifying code or virtual
1184 to physical address re-mapping, Cortex-A8 does not recover from the
1185 stale interworking branch prediction. This results in Cortex-A8
1186 executing the new code sequence in the incorrect ARM or Thumb state.
1187 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1188 and also flushes the branch target cache at every context switch.
1189 Note that setting specific bits in the ACTLR register may not be
1190 available in non-secure mode.
1192 config ARM_ERRATA_458693
1193 bool "ARM errata: Processor deadlock when a false hazard is created"
1196 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1197 erratum. For very specific sequences of memory operations, it is
1198 possible for a hazard condition intended for a cache line to instead
1199 be incorrectly associated with a different cache line. This false
1200 hazard might then cause a processor deadlock. The workaround enables
1201 the L1 caching of the NEON accesses and disables the PLD instruction
1202 in the ACTLR register. Note that setting specific bits in the ACTLR
1203 register may not be available in non-secure mode.
1205 config ARM_ERRATA_460075
1206 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1209 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1210 erratum. Any asynchronous access to the L2 cache may encounter a
1211 situation in which recent store transactions to the L2 cache are lost
1212 and overwritten with stale memory contents from external memory. The
1213 workaround disables the write-allocate mode for the L2 cache via the
1214 ACTLR register. Note that setting specific bits in the ACTLR register
1215 may not be available in non-secure mode.
1217 config ARM_ERRATA_742230
1218 bool "ARM errata: DMB operation may be faulty"
1219 depends on CPU_V7 && SMP
1221 This option enables the workaround for the 742230 Cortex-A9
1222 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1223 between two write operations may not ensure the correct visibility
1224 ordering of the two writes. This workaround sets a specific bit in
1225 the diagnostic register of the Cortex-A9 which causes the DMB
1226 instruction to behave as a DSB, ensuring the correct behaviour of
1229 config ARM_ERRATA_742231
1230 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1231 depends on CPU_V7 && SMP
1233 This option enables the workaround for the 742231 Cortex-A9
1234 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1235 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1236 accessing some data located in the same cache line, may get corrupted
1237 data due to bad handling of the address hazard when the line gets
1238 replaced from one of the CPUs at the same time as another CPU is
1239 accessing it. This workaround sets specific bits in the diagnostic
1240 register of the Cortex-A9 which reduces the linefill issuing
1241 capabilities of the processor.
1243 config PL310_ERRATA_588369
1244 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1245 depends on CACHE_L2X0
1247 The PL310 L2 cache controller implements three types of Clean &
1248 Invalidate maintenance operations: by Physical Address
1249 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1250 They are architecturally defined to behave as the execution of a
1251 clean operation followed immediately by an invalidate operation,
1252 both performing to the same memory location. This functionality
1253 is not correctly implemented in PL310 as clean lines are not
1254 invalidated as a result of these operations.
1256 config ARM_ERRATA_720789
1257 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1260 This option enables the workaround for the 720789 Cortex-A9 (prior to
1261 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1262 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1263 As a consequence of this erratum, some TLB entries which should be
1264 invalidated are not, resulting in an incoherency in the system page
1265 tables. The workaround changes the TLB flushing routines to invalidate
1266 entries regardless of the ASID.
1268 config PL310_ERRATA_727915
1269 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1270 depends on CACHE_L2X0
1272 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1273 operation (offset 0x7FC). This operation runs in background so that
1274 PL310 can handle normal accesses while it is in progress. Under very
1275 rare circumstances, due to this erratum, write data can be lost when
1276 PL310 treats a cacheable write transaction during a Clean &
1277 Invalidate by Way operation.
1279 config ARM_ERRATA_743622
1280 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1283 This option enables the workaround for the 743622 Cortex-A9
1284 (r2p*) erratum. Under very rare conditions, a faulty
1285 optimisation in the Cortex-A9 Store Buffer may lead to data
1286 corruption. This workaround sets a specific bit in the diagnostic
1287 register of the Cortex-A9 which disables the Store Buffer
1288 optimisation, preventing the defect from occurring. This has no
1289 visible impact on the overall performance or power consumption of the
1292 config ARM_ERRATA_751472
1293 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1296 This option enables the workaround for the 751472 Cortex-A9 (prior
1297 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1298 completion of a following broadcasted operation if the second
1299 operation is received by a CPU before the ICIALLUIS has completed,
1300 potentially leading to corrupted entries in the cache or TLB.
1302 config PL310_ERRATA_753970
1303 bool "PL310 errata: cache sync operation may be faulty"
1304 depends on CACHE_PL310
1306 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1308 Under some condition the effect of cache sync operation on
1309 the store buffer still remains when the operation completes.
1310 This means that the store buffer is always asked to drain and
1311 this prevents it from merging any further writes. The workaround
1312 is to replace the normal offset of cache sync operation (0x730)
1313 by another offset targeting an unmapped PL310 register 0x740.
1314 This has the same effect as the cache sync operation: store buffer
1315 drain and waiting for all buffers empty.
1317 config ARM_ERRATA_754322
1318 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1321 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1322 r3p*) erratum. A speculative memory access may cause a page table walk
1323 which starts prior to an ASID switch but completes afterwards. This
1324 can populate the micro-TLB with a stale entry which may be hit with
1325 the new ASID. This workaround places two dsb instructions in the mm
1326 switching code so that no page table walks can cross the ASID switch.
1328 config ARM_ERRATA_754327
1329 bool "ARM errata: no automatic Store Buffer drain"
1330 depends on CPU_V7 && SMP
1332 This option enables the workaround for the 754327 Cortex-A9 (prior to
1333 r2p0) erratum. The Store Buffer does not have any automatic draining
1334 mechanism and therefore a livelock may occur if an external agent
1335 continuously polls a memory location waiting to observe an update.
1336 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1337 written polling loops from denying visibility of updates to memory.
1339 config ARM_ERRATA_364296
1340 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1341 depends on CPU_V6 && !SMP
1343 This options enables the workaround for the 364296 ARM1136
1344 r0p2 erratum (possible cache data corruption with
1345 hit-under-miss enabled). It sets the undocumented bit 31 in
1346 the auxiliary control register and the FI bit in the control
1347 register, thus disabling hit-under-miss without putting the
1348 processor into full low interrupt latency mode. ARM11MPCore
1351 config ARM_ERRATA_764369
1352 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1353 depends on CPU_V7 && SMP
1355 This option enables the workaround for erratum 764369
1356 affecting Cortex-A9 MPCore with two or more processors (all
1357 current revisions). Under certain timing circumstances, a data
1358 cache line maintenance operation by MVA targeting an Inner
1359 Shareable memory region may fail to proceed up to either the
1360 Point of Coherency or to the Point of Unification of the
1361 system. This workaround adds a DSB instruction before the
1362 relevant cache maintenance functions and sets a specific bit
1363 in the diagnostic control register of the SCU.
1365 config PL310_ERRATA_769419
1366 bool "PL310 errata: no automatic Store Buffer drain"
1367 depends on CACHE_L2X0
1369 On revisions of the PL310 prior to r3p2, the Store Buffer does
1370 not automatically drain. This can cause normal, non-cacheable
1371 writes to be retained when the memory system is idle, leading
1372 to suboptimal I/O performance for drivers using coherent DMA.
1373 This option adds a write barrier to the cpu_idle loop so that,
1374 on systems with an outer cache, the store buffer is drained
1379 source "arch/arm/common/Kconfig"
1389 Find out whether you have ISA slots on your motherboard. ISA is the
1390 name of a bus system, i.e. the way the CPU talks to the other stuff
1391 inside your box. Other bus systems are PCI, EISA, MicroChannel
1392 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1393 newer boards don't support it. If you have ISA, say Y, otherwise N.
1395 # Select ISA DMA controller support
1400 # Select ISA DMA interface
1405 bool "PCI support" if MIGHT_HAVE_PCI
1407 Find out whether you have a PCI motherboard. PCI is the name of a
1408 bus system, i.e. the way the CPU talks to the other stuff inside
1409 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1410 VESA. If you have PCI, say Y, otherwise N.
1416 config PCI_NANOENGINE
1417 bool "BSE nanoEngine PCI support"
1418 depends on SA1100_NANOENGINE
1420 Enable PCI on the BSE nanoEngine board.
1425 # Select the host bridge type
1426 config PCI_HOST_VIA82C505
1428 depends on PCI && ARCH_SHARK
1431 config PCI_HOST_ITE8152
1433 depends on PCI && MACH_ARMCORE
1437 source "drivers/pci/Kconfig"
1439 source "drivers/pcmcia/Kconfig"
1443 menu "Kernel Features"
1448 This option should be selected by machines which have an SMP-
1451 The only effect of this option is to make the SMP-related
1452 options available to the user for configuration.
1455 bool "Symmetric Multi-Processing"
1456 depends on CPU_V6K || CPU_V7
1457 depends on GENERIC_CLOCKEVENTS
1460 select USE_GENERIC_SMP_HELPERS
1461 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1463 This enables support for systems with more than one CPU. If you have
1464 a system with only one CPU, like most personal computers, say N. If
1465 you have a system with more than one CPU, say Y.
1467 If you say N here, the kernel will run on single and multiprocessor
1468 machines, but will use only one CPU of a multiprocessor machine. If
1469 you say Y here, the kernel will run on many, but not all, single
1470 processor machines. On a single processor machine, the kernel will
1471 run faster if you say N here.
1473 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1474 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1475 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1477 If you don't know what to do here, say N.
1480 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1481 depends on EXPERIMENTAL
1482 depends on SMP && !XIP_KERNEL
1485 SMP kernels contain instructions which fail on non-SMP processors.
1486 Enabling this option allows the kernel to modify itself to make
1487 these instructions safe. Disabling it allows about 1K of space
1490 If you don't know what to do here, say Y.
1492 config ARM_CPU_TOPOLOGY
1493 bool "Support cpu topology definition"
1494 depends on SMP && CPU_V7
1497 Support ARM cpu topology definition. The MPIDR register defines
1498 affinity between processors which is then used to describe the cpu
1499 topology of an ARM System.
1502 bool "Multi-core scheduler support"
1503 depends on ARM_CPU_TOPOLOGY
1505 Multi-core scheduler support improves the CPU scheduler's decision
1506 making when dealing with multi-core CPU chips at a cost of slightly
1507 increased overhead in some places. If unsure say N here.
1510 bool "SMT scheduler support"
1511 depends on ARM_CPU_TOPOLOGY
1513 Improves the CPU scheduler's decision making when dealing with
1514 MultiThreading at a cost of slightly increased overhead in some
1515 places. If unsure say N here.
1520 This option enables support for the ARM system coherency unit
1522 config ARM_ARCH_TIMER
1523 bool "Architected timer support"
1526 This option enables support for the ARM architected timer
1532 This options enables support for the ARM timer and watchdog unit
1535 prompt "Memory split"
1538 Select the desired split between kernel and user memory.
1540 If you are not absolutely sure what you are doing, leave this
1544 bool "3G/1G user/kernel split"
1546 bool "2G/2G user/kernel split"
1548 bool "1G/3G user/kernel split"
1553 default 0x40000000 if VMSPLIT_1G
1554 default 0x80000000 if VMSPLIT_2G
1558 int "Maximum number of CPUs (2-32)"
1564 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1565 depends on SMP && HOTPLUG && EXPERIMENTAL
1567 Say Y here to experiment with turning CPUs off and on. CPUs
1568 can be controlled through /sys/devices/system/cpu.
1571 bool "Use local timer interrupts"
1574 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1576 Enable support for local timers on SMP platforms, rather then the
1577 legacy IPI broadcast method. Local timers allows the system
1578 accounting to be spread across the timer interval, preventing a
1579 "thundering herd" at every timer tick.
1583 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1584 default 355 if ARCH_U8500
1585 default 264 if MACH_H4700
1588 Maximum number of GPIOs in the system.
1590 If unsure, leave the default value.
1592 source kernel/Kconfig.preempt
1596 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1597 ARCH_S5PV210 || ARCH_EXYNOS4
1598 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1599 default AT91_TIMER_HZ if ARCH_AT91
1600 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1603 config THUMB2_KERNEL
1604 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1605 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1607 select ARM_ASM_UNIFIED
1610 By enabling this option, the kernel will be compiled in
1611 Thumb-2 mode. A compiler/assembler that understand the unified
1612 ARM-Thumb syntax is needed.
1616 config THUMB2_AVOID_R_ARM_THM_JUMP11
1617 bool "Work around buggy Thumb-2 short branch relocations in gas"
1618 depends on THUMB2_KERNEL && MODULES
1621 Various binutils versions can resolve Thumb-2 branches to
1622 locally-defined, preemptible global symbols as short-range "b.n"
1623 branch instructions.
1625 This is a problem, because there's no guarantee the final
1626 destination of the symbol, or any candidate locations for a
1627 trampoline, are within range of the branch. For this reason, the
1628 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1629 relocation in modules at all, and it makes little sense to add
1632 The symptom is that the kernel fails with an "unsupported
1633 relocation" error when loading some modules.
1635 Until fixed tools are available, passing
1636 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1637 code which hits this problem, at the cost of a bit of extra runtime
1638 stack usage in some cases.
1640 The problem is described in more detail at:
1641 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1643 Only Thumb-2 kernels are affected.
1645 Unless you are sure your tools don't have this problem, say Y.
1647 config ARM_ASM_UNIFIED
1651 bool "Use the ARM EABI to compile the kernel"
1653 This option allows for the kernel to be compiled using the latest
1654 ARM ABI (aka EABI). This is only useful if you are using a user
1655 space environment that is also compiled with EABI.
1657 Since there are major incompatibilities between the legacy ABI and
1658 EABI, especially with regard to structure member alignment, this
1659 option also changes the kernel syscall calling convention to
1660 disambiguate both ABIs and allow for backward compatibility support
1661 (selected with CONFIG_OABI_COMPAT).
1663 To use this you need GCC version 4.0.0 or later.
1666 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1667 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1670 This option preserves the old syscall interface along with the
1671 new (ARM EABI) one. It also provides a compatibility layer to
1672 intercept syscalls that have structure arguments which layout
1673 in memory differs between the legacy ABI and the new ARM EABI
1674 (only for non "thumb" binaries). This option adds a tiny
1675 overhead to all syscalls and produces a slightly larger kernel.
1676 If you know you'll be using only pure EABI user space then you
1677 can say N here. If this option is not selected and you attempt
1678 to execute a legacy ABI binary then the result will be
1679 UNPREDICTABLE (in fact it can be predicted that it won't work
1680 at all). If in doubt say Y.
1682 config ARCH_HAS_HOLES_MEMORYMODEL
1685 config ARCH_SPARSEMEM_ENABLE
1688 config ARCH_SPARSEMEM_DEFAULT
1689 def_bool ARCH_SPARSEMEM_ENABLE
1691 config ARCH_SELECT_MEMORY_MODEL
1692 def_bool ARCH_SPARSEMEM_ENABLE
1694 config HAVE_ARCH_PFN_VALID
1695 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1698 bool "High Memory Support"
1701 The address space of ARM processors is only 4 Gigabytes large
1702 and it has to accommodate user address space, kernel address
1703 space as well as some memory mapped IO. That means that, if you
1704 have a large amount of physical memory and/or IO, not all of the
1705 memory can be "permanently mapped" by the kernel. The physical
1706 memory that is not permanently mapped is called "high memory".
1708 Depending on the selected kernel/user memory split, minimum
1709 vmalloc space and actual amount of RAM, you may not need this
1710 option which should result in a slightly faster kernel.
1715 bool "Allocate 2nd-level pagetables from highmem"
1718 config HW_PERF_EVENTS
1719 bool "Enable hardware performance counter support for perf events"
1720 depends on PERF_EVENTS && CPU_HAS_PMU
1723 Enable hardware performance counter support for perf events. If
1724 disabled, perf events will use software events only.
1728 config FORCE_MAX_ZONEORDER
1729 int "Maximum zone order" if ARCH_SHMOBILE
1730 range 11 64 if ARCH_SHMOBILE
1731 default "9" if SA1111
1734 The kernel memory allocator divides physically contiguous memory
1735 blocks into "zones", where each zone is a power of two number of
1736 pages. This option selects the largest power of two that the kernel
1737 keeps in the memory allocator. If you need to allocate very large
1738 blocks of physically contiguous memory, then you may need to
1739 increase this value.
1741 This config option is actually maximum order plus one. For example,
1742 a value of 11 means that the largest free memory block is 2^10 pages.
1745 bool "Timer and CPU usage LEDs"
1746 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1747 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1748 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1749 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1750 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1751 ARCH_AT91 || ARCH_DAVINCI || \
1752 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1754 If you say Y here, the LEDs on your machine will be used
1755 to provide useful information about your current system status.
1757 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1758 be able to select which LEDs are active using the options below. If
1759 you are compiling a kernel for the EBSA-110 or the LART however, the
1760 red LED will simply flash regularly to indicate that the system is
1761 still functional. It is safe to say Y here if you have a CATS
1762 system, but the driver will do nothing.
1765 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1766 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1767 || MACH_OMAP_PERSEUS2
1769 depends on !GENERIC_CLOCKEVENTS
1770 default y if ARCH_EBSA110
1772 If you say Y here, one of the system LEDs (the green one on the
1773 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1774 will flash regularly to indicate that the system is still
1775 operational. This is mainly useful to kernel hackers who are
1776 debugging unstable kernels.
1778 The LART uses the same LED for both Timer LED and CPU usage LED
1779 functions. You may choose to use both, but the Timer LED function
1780 will overrule the CPU usage LED.
1783 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1785 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1786 || MACH_OMAP_PERSEUS2
1789 If you say Y here, the red LED will be used to give a good real
1790 time indication of CPU usage, by lighting whenever the idle task
1791 is not currently executing.
1793 The LART uses the same LED for both Timer LED and CPU usage LED
1794 functions. You may choose to use both, but the Timer LED function
1795 will overrule the CPU usage LED.
1797 config ALIGNMENT_TRAP
1799 depends on CPU_CP15_MMU
1800 default y if !ARCH_EBSA110
1801 select HAVE_PROC_CPU if PROC_FS
1803 ARM processors cannot fetch/store information which is not
1804 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1805 address divisible by 4. On 32-bit ARM processors, these non-aligned
1806 fetch/store instructions will be emulated in software if you say
1807 here, which has a severe performance impact. This is necessary for
1808 correct operation of some network protocols. With an IP-only
1809 configuration it is safe to say N, otherwise say Y.
1811 config UACCESS_WITH_MEMCPY
1812 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1813 depends on MMU && EXPERIMENTAL
1814 default y if CPU_FEROCEON
1816 Implement faster copy_to_user and clear_user methods for CPU
1817 cores where a 8-word STM instruction give significantly higher
1818 memory write throughput than a sequence of individual 32bit stores.
1820 A possible side effect is a slight increase in scheduling latency
1821 between threads sharing the same address space if they invoke
1822 such copy operations with large buffers.
1824 However, if the CPU data cache is using a write-allocate mode,
1825 this option is unlikely to provide any performance gain.
1829 prompt "Enable seccomp to safely compute untrusted bytecode"
1831 This kernel feature is useful for number crunching applications
1832 that may need to compute untrusted bytecode during their
1833 execution. By using pipes or other transports made available to
1834 the process as file descriptors supporting the read/write
1835 syscalls, it's possible to isolate those applications in
1836 their own address space using seccomp. Once seccomp is
1837 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1838 and the task is only allowed to execute a few safe syscalls
1839 defined by each seccomp mode.
1841 config CC_STACKPROTECTOR
1842 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1843 depends on EXPERIMENTAL
1845 This option turns on the -fstack-protector GCC feature. This
1846 feature puts, at the beginning of functions, a canary value on
1847 the stack just before the return address, and validates
1848 the value just before actually returning. Stack based buffer
1849 overflows (that need to overwrite this return address) now also
1850 overwrite the canary, which gets detected and the attack is then
1851 neutralized via a kernel panic.
1852 This feature requires gcc version 4.2 or above.
1854 config DEPRECATED_PARAM_STRUCT
1855 bool "Provide old way to pass kernel parameters"
1857 This was deprecated in 2001 and announced to live on for 5 years.
1858 Some old boot loaders still use this way.
1865 bool "Flattened Device Tree support"
1867 select OF_EARLY_FLATTREE
1870 Include support for flattened device tree machine descriptions.
1872 # Compressed boot loader in ROM. Yes, we really want to ask about
1873 # TEXT and BSS so we preserve their values in the config files.
1874 config ZBOOT_ROM_TEXT
1875 hex "Compressed ROM boot loader base address"
1878 The physical address at which the ROM-able zImage is to be
1879 placed in the target. Platforms which normally make use of
1880 ROM-able zImage formats normally set this to a suitable
1881 value in their defconfig file.
1883 If ZBOOT_ROM is not enabled, this has no effect.
1885 config ZBOOT_ROM_BSS
1886 hex "Compressed ROM boot loader BSS address"
1889 The base address of an area of read/write memory in the target
1890 for the ROM-able zImage which must be available while the
1891 decompressor is running. It must be large enough to hold the
1892 entire decompressed kernel plus an additional 128 KiB.
1893 Platforms which normally make use of ROM-able zImage formats
1894 normally set this to a suitable value in their defconfig file.
1896 If ZBOOT_ROM is not enabled, this has no effect.
1899 bool "Compressed boot loader in ROM/flash"
1900 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1902 Say Y here if you intend to execute your compressed kernel image
1903 (zImage) directly from ROM or flash. If unsure, say N.
1906 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1907 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1908 default ZBOOT_ROM_NONE
1910 Include experimental SD/MMC loading code in the ROM-able zImage.
1911 With this enabled it is possible to write the ROM-able zImage
1912 kernel image to an MMC or SD card and boot the kernel straight
1913 from the reset vector. At reset the processor Mask ROM will load
1914 the first part of the ROM-able zImage which in turn loads the
1915 rest the kernel image to RAM.
1917 config ZBOOT_ROM_NONE
1918 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1920 Do not load image from SD or MMC
1922 config ZBOOT_ROM_MMCIF
1923 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1925 Load image from MMCIF hardware block.
1927 config ZBOOT_ROM_SH_MOBILE_SDHI
1928 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1930 Load image from SDHI hardware block
1934 config ARM_APPENDED_DTB
1935 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1936 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1938 With this option, the boot code will look for a device tree binary
1939 (DTB) appended to zImage
1940 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1942 This is meant as a backward compatibility convenience for those
1943 systems with a bootloader that can't be upgraded to accommodate
1944 the documented boot protocol using a device tree.
1946 Beware that there is very little in terms of protection against
1947 this option being confused by leftover garbage in memory that might
1948 look like a DTB header after a reboot if no actual DTB is appended
1949 to zImage. Do not leave this option active in a production kernel
1950 if you don't intend to always append a DTB. Proper passing of the
1951 location into r2 of a bootloader provided DTB is always preferable
1954 config ARM_ATAG_DTB_COMPAT
1955 bool "Supplement the appended DTB with traditional ATAG information"
1956 depends on ARM_APPENDED_DTB
1958 Some old bootloaders can't be updated to a DTB capable one, yet
1959 they provide ATAGs with memory configuration, the ramdisk address,
1960 the kernel cmdline string, etc. Such information is dynamically
1961 provided by the bootloader and can't always be stored in a static
1962 DTB. To allow a device tree enabled kernel to be used with such
1963 bootloaders, this option allows zImage to extract the information
1964 from the ATAG list and store it at run time into the appended DTB.
1967 string "Default kernel command string"
1970 On some architectures (EBSA110 and CATS), there is currently no way
1971 for the boot loader to pass arguments to the kernel. For these
1972 architectures, you should supply some command-line options at build
1973 time by entering them here. As a minimum, you should specify the
1974 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1977 prompt "Kernel command line type" if CMDLINE != ""
1978 default CMDLINE_FROM_BOOTLOADER
1980 config CMDLINE_FROM_BOOTLOADER
1981 bool "Use bootloader kernel arguments if available"
1983 Uses the command-line options passed by the boot loader. If
1984 the boot loader doesn't provide any, the default kernel command
1985 string provided in CMDLINE will be used.
1987 config CMDLINE_EXTEND
1988 bool "Extend bootloader kernel arguments"
1990 The command-line arguments provided by the boot loader will be
1991 appended to the default kernel command string.
1993 config CMDLINE_FORCE
1994 bool "Always use the default kernel command string"
1996 Always use the default kernel command string, even if the boot
1997 loader passes other arguments to the kernel.
1998 This is useful if you cannot or don't want to change the
1999 command-line options your boot loader passes to the kernel.
2003 bool "Kernel Execute-In-Place from ROM"
2004 depends on !ZBOOT_ROM && !ARM_LPAE
2006 Execute-In-Place allows the kernel to run from non-volatile storage
2007 directly addressable by the CPU, such as NOR flash. This saves RAM
2008 space since the text section of the kernel is not loaded from flash
2009 to RAM. Read-write sections, such as the data section and stack,
2010 are still copied to RAM. The XIP kernel is not compressed since
2011 it has to run directly from flash, so it will take more space to
2012 store it. The flash address used to link the kernel object files,
2013 and for storing it, is configuration dependent. Therefore, if you
2014 say Y here, you must know the proper physical address where to
2015 store the kernel image depending on your own flash memory usage.
2017 Also note that the make target becomes "make xipImage" rather than
2018 "make zImage" or "make Image". The final kernel binary to put in
2019 ROM memory will be arch/arm/boot/xipImage.
2023 config XIP_PHYS_ADDR
2024 hex "XIP Kernel Physical Location"
2025 depends on XIP_KERNEL
2026 default "0x00080000"
2028 This is the physical address in your flash memory the kernel will
2029 be linked for and stored to. This address is dependent on your
2033 bool "Kexec system call (EXPERIMENTAL)"
2034 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2036 kexec is a system call that implements the ability to shutdown your
2037 current kernel, and to start another kernel. It is like a reboot
2038 but it is independent of the system firmware. And like a reboot
2039 you can start any kernel with it, not just Linux.
2041 It is an ongoing process to be certain the hardware in a machine
2042 is properly shutdown, so do not be surprised if this code does not
2043 initially work for you. It may help to enable device hotplugging
2047 bool "Export atags in procfs"
2051 Should the atags used to boot the kernel be exported in an "atags"
2052 file in procfs. Useful with kexec.
2055 bool "Build kdump crash kernel (EXPERIMENTAL)"
2056 depends on EXPERIMENTAL
2058 Generate crash dump after being started by kexec. This should
2059 be normally only set in special crash dump kernels which are
2060 loaded in the main kernel with kexec-tools into a specially
2061 reserved region and then later executed after a crash by
2062 kdump/kexec. The crash dump kernel must be compiled to a
2063 memory address not used by the main kernel
2065 For more details see Documentation/kdump/kdump.txt
2067 config AUTO_ZRELADDR
2068 bool "Auto calculation of the decompressed kernel image address"
2069 depends on !ZBOOT_ROM && !ARCH_U300
2071 ZRELADDR is the physical address where the decompressed kernel
2072 image will be placed. If AUTO_ZRELADDR is selected, the address
2073 will be determined at run-time by masking the current IP with
2074 0xf8000000. This assumes the zImage being placed in the first 128MB
2075 from start of memory.
2079 menu "CPU Power Management"
2083 source "drivers/cpufreq/Kconfig"
2086 tristate "CPUfreq driver for i.MX CPUs"
2087 depends on ARCH_MXC && CPU_FREQ
2089 This enables the CPUfreq driver for i.MX CPUs.
2091 config CPU_FREQ_SA1100
2094 config CPU_FREQ_SA1110
2097 config CPU_FREQ_INTEGRATOR
2098 tristate "CPUfreq driver for ARM Integrator CPUs"
2099 depends on ARCH_INTEGRATOR && CPU_FREQ
2102 This enables the CPUfreq driver for ARM Integrator CPUs.
2104 For details, take a look at <file:Documentation/cpu-freq>.
2110 depends on CPU_FREQ && ARCH_PXA && PXA25x
2112 select CPU_FREQ_TABLE
2113 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2118 Internal configuration node for common cpufreq on Samsung SoC
2120 config CPU_FREQ_S3C24XX
2121 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2122 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2125 This enables the CPUfreq driver for the Samsung S3C24XX family
2128 For details, take a look at <file:Documentation/cpu-freq>.
2132 config CPU_FREQ_S3C24XX_PLL
2133 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2134 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2136 Compile in support for changing the PLL frequency from the
2137 S3C24XX series CPUfreq driver. The PLL takes time to settle
2138 after a frequency change, so by default it is not enabled.
2140 This also means that the PLL tables for the selected CPU(s) will
2141 be built which may increase the size of the kernel image.
2143 config CPU_FREQ_S3C24XX_DEBUG
2144 bool "Debug CPUfreq Samsung driver core"
2145 depends on CPU_FREQ_S3C24XX
2147 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2149 config CPU_FREQ_S3C24XX_IODEBUG
2150 bool "Debug CPUfreq Samsung driver IO timing"
2151 depends on CPU_FREQ_S3C24XX
2153 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2155 config CPU_FREQ_S3C24XX_DEBUGFS
2156 bool "Export debugfs for CPUFreq"
2157 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2159 Export status information via debugfs.
2163 source "drivers/cpuidle/Kconfig"
2167 menu "Floating point emulation"
2169 comment "At least one emulation must be selected"
2172 bool "NWFPE math emulation"
2173 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2175 Say Y to include the NWFPE floating point emulator in the kernel.
2176 This is necessary to run most binaries. Linux does not currently
2177 support floating point hardware so you need to say Y here even if
2178 your machine has an FPA or floating point co-processor podule.
2180 You may say N here if you are going to load the Acorn FPEmulator
2181 early in the bootup.
2184 bool "Support extended precision"
2185 depends on FPE_NWFPE
2187 Say Y to include 80-bit support in the kernel floating-point
2188 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2189 Note that gcc does not generate 80-bit operations by default,
2190 so in most cases this option only enlarges the size of the
2191 floating point emulator without any good reason.
2193 You almost surely want to say N here.
2196 bool "FastFPE math emulation (EXPERIMENTAL)"
2197 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2199 Say Y here to include the FAST floating point emulator in the kernel.
2200 This is an experimental much faster emulator which now also has full
2201 precision for the mantissa. It does not support any exceptions.
2202 It is very simple, and approximately 3-6 times faster than NWFPE.
2204 It should be sufficient for most programs. It may be not suitable
2205 for scientific calculations, but you have to check this for yourself.
2206 If you do not feel you need a faster FP emulation you should better
2210 bool "VFP-format floating point maths"
2211 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2213 Say Y to include VFP support code in the kernel. This is needed
2214 if your hardware includes a VFP unit.
2216 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2217 release notes and additional status information.
2219 Say N if your target does not have VFP hardware.
2227 bool "Advanced SIMD (NEON) Extension support"
2228 depends on VFPv3 && CPU_V7
2230 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2235 menu "Userspace binary formats"
2237 source "fs/Kconfig.binfmt"
2240 tristate "RISC OS personality"
2243 Say Y here to include the kernel code necessary if you want to run
2244 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2245 experimental; if this sounds frightening, say N and sleep in peace.
2246 You can also say M here to compile this support as a module (which
2247 will be called arthur).
2251 menu "Power management options"
2253 source "kernel/power/Kconfig"
2255 config ARCH_SUSPEND_POSSIBLE
2256 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2257 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2258 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2261 config ARM_CPU_SUSPEND
2266 source "net/Kconfig"
2268 source "drivers/Kconfig"
2272 source "arch/arm/Kconfig.debug"
2274 source "security/Kconfig"
2276 source "crypto/Kconfig"
2278 source "lib/Kconfig"