4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
254 bool "Altera SOCFPGA family"
255 select ARCH_WANT_OPTIONAL_GPIOLIB
263 select DW_APB_TIMER_OF
264 select GENERIC_CLOCKEVENTS
265 select GPIO_PL061 if GPIOLIB
270 This enables support for Altera SOCFPGA Cyclone V platform
272 config ARCH_INTEGRATOR
273 bool "ARM Ltd. Integrator family"
275 select ARCH_HAS_CPUFREQ
277 select HAVE_MACH_CLKDEV
280 select GENERIC_CLOCKEVENTS
281 select PLAT_VERSATILE
282 select PLAT_VERSATILE_CLOCK
283 select PLAT_VERSATILE_FPGA_IRQ
284 select NEED_MACH_IO_H
285 select NEED_MACH_MEMORY_H
287 select MULTI_IRQ_HANDLER
289 Support for ARM's Integrator platform.
292 bool "ARM Ltd. RealView family"
295 select HAVE_MACH_CLKDEV
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
301 select PLAT_VERSATILE_CLCD
302 select ARM_TIMER_SP804
303 select GPIO_PL061 if GPIOLIB
304 select NEED_MACH_MEMORY_H
306 This enables support for ARM Ltd RealView boards.
308 config ARCH_VERSATILE
309 bool "ARM Ltd. Versatile family"
313 select HAVE_MACH_CLKDEV
315 select GENERIC_CLOCKEVENTS
316 select ARCH_WANT_OPTIONAL_GPIOLIB
317 select NEED_MACH_IO_H if PCI
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLOCK
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_FPGA_IRQ
322 select ARM_TIMER_SP804
324 This enables support for ARM Ltd Versatile board.
327 bool "ARM Ltd. Versatile Express family"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 select ARM_TIMER_SP804
333 select GENERIC_CLOCKEVENTS
335 select HAVE_PATA_PLATFORM
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLCD
340 select REGULATOR_FIXED_VOLTAGE if REGULATOR
342 This enables support for the ARM Ltd Versatile Express boards.
346 select ARCH_REQUIRE_GPIOLIB
350 select NEED_MACH_IO_H if PCCARD
352 This enables support for systems based on Atmel
353 AT91RM9200 and AT91SAM9* processors.
356 bool "Broadcom BCMRING"
360 select ARM_TIMER_SP804
362 select GENERIC_CLOCKEVENTS
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 Support for Broadcom's BCMRing platform.
368 bool "Calxeda Highbank-based"
369 select ARCH_WANT_OPTIONAL_GPIOLIB
372 select ARM_TIMER_SP804
376 select GENERIC_CLOCKEVENTS
382 Support for the Calxeda Highbank SoC based boards.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
387 select ARCH_USES_GETTIMEOFFSET
388 select NEED_MACH_MEMORY_H
390 Support for Cirrus Logic 711x/721x/731x based boards.
393 bool "Cavium Networks CNS3XXX family"
395 select GENERIC_CLOCKEVENTS
397 select MIGHT_HAVE_CACHE_L2X0
398 select MIGHT_HAVE_PCI
399 select PCI_DOMAINS if PCI
401 Support for Cavium Networks CNS3XXX platform.
404 bool "Cortina Systems Gemini"
406 select ARCH_REQUIRE_GPIOLIB
407 select ARCH_USES_GETTIMEOFFSET
409 Support for the Cortina Systems Gemini family SoCs
412 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
415 select GENERIC_CLOCKEVENTS
417 select GENERIC_IRQ_CHIP
418 select MIGHT_HAVE_CACHE_L2X0
424 Support for CSR SiRFSoC ARM Cortex A9 Platform
431 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_IO_H
433 select NEED_MACH_MEMORY_H
435 This is an evaluation board for the StrongARM processor available
436 from Digital. It has limited hardware on-board, including an
437 Ethernet interface, two PCMCIA sockets, two serial ports and a
446 select ARCH_REQUIRE_GPIOLIB
447 select ARCH_HAS_HOLES_MEMORYMODEL
448 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Freescale MXC/iMX-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
471 select GENERIC_IRQ_CHIP
472 select MULTI_IRQ_HANDLER
474 Support for Freescale MXC/iMX-based family of processors
477 bool "Freescale MXS-based"
478 select GENERIC_CLOCKEVENTS
479 select ARCH_REQUIRE_GPIOLIB
483 select HAVE_CLK_PREPARE
487 Support for Freescale MXS-based family of processors
490 bool "Hilscher NetX based"
494 select GENERIC_CLOCKEVENTS
496 This enables support for systems based on the Hilscher NetX Soc
499 bool "Hynix HMS720x-based"
502 select ARCH_USES_GETTIMEOFFSET
504 This enables support for systems based on the Hynix HMS720x
512 select ARCH_SUPPORTS_MSI
514 select NEED_MACH_IO_H
515 select NEED_MACH_MEMORY_H
516 select NEED_RET_TO_USER
518 Support for Intel's IOP13XX (XScale) family of processors.
524 select NEED_MACH_IO_H
525 select NEED_RET_TO_USER
528 select ARCH_REQUIRE_GPIOLIB
530 Support for Intel's 80219 and IOP32X (XScale) family of
537 select NEED_MACH_IO_H
538 select NEED_RET_TO_USER
541 select ARCH_REQUIRE_GPIOLIB
543 Support for Intel's IOP33X (XScale) family of processors.
548 select ARCH_HAS_DMA_SET_COHERENT_MASK
551 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
553 select MIGHT_HAVE_PCI
554 select NEED_MACH_IO_H
555 select DMABOUNCE if PCI
557 Support for Intel's IXP4XX (XScale) family of processors.
560 bool "Marvell SOCs with Device Tree support"
561 select GENERIC_CLOCKEVENTS
562 select MULTI_IRQ_HANDLER
565 select GENERIC_IRQ_CHIP
569 Support for the Marvell SoC Family with device tree support
575 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
577 select NEED_MACH_IO_H
580 Support for the Marvell Dove SoC 88AP510
583 bool "Marvell Kirkwood"
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
588 select NEED_MACH_IO_H
591 Support for the following Marvell Kirkwood series SoCs:
592 88F6180, 88F6192 and 88F6281.
598 select ARCH_REQUIRE_GPIOLIB
601 select USB_ARCH_HAS_OHCI
603 select GENERIC_CLOCKEVENTS
607 Support for the NXP LPC32XX family of processors
610 bool "Marvell MV78xx0"
613 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
615 select NEED_MACH_IO_H
618 Support for the following Marvell MV78xx0 series SoCs:
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
628 select NEED_MACH_IO_H
631 Support for the following Marvell Orion 5x series SoCs:
632 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
633 Orion-2 (5281), Orion-1-90 (6183).
636 bool "Marvell PXA168/910/MMP2"
638 select ARCH_REQUIRE_GPIOLIB
640 select GENERIC_CLOCKEVENTS
645 select GENERIC_ALLOCATOR
647 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
650 bool "Micrel/Kendin KS8695"
652 select ARCH_REQUIRE_GPIOLIB
653 select ARCH_USES_GETTIMEOFFSET
654 select NEED_MACH_MEMORY_H
656 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
657 System-on-Chip devices.
660 bool "Nuvoton W90X900 CPU"
662 select ARCH_REQUIRE_GPIOLIB
665 select GENERIC_CLOCKEVENTS
667 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
668 At present, the w90x900 has been renamed nuc900, regarding
669 the ARM series product line, you can login the following
670 link address to know more.
672 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
673 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
679 select GENERIC_CLOCKEVENTS
683 select MIGHT_HAVE_CACHE_L2X0
684 select NEED_MACH_IO_H if PCI
685 select ARCH_HAS_CPUFREQ
687 This enables support for NVIDIA Tegra based systems (Tegra APX,
688 Tegra 6xx and Tegra 2 series).
690 config ARCH_PICOXCELL
691 bool "Picochip picoXcell"
692 select ARCH_REQUIRE_GPIOLIB
693 select ARM_PATCH_PHYS_VIRT
697 select DW_APB_TIMER_OF
698 select GENERIC_CLOCKEVENTS
705 This enables support for systems based on the Picochip picoXcell
706 family of Femtocell devices. The picoxcell support requires device tree
710 bool "Philips Nexperia PNX4008 Mobile"
713 select ARCH_USES_GETTIMEOFFSET
715 This enables support for Philips PNX4008 mobile platform.
718 bool "PXA2xx/PXA3xx-based"
721 select ARCH_HAS_CPUFREQ
724 select ARCH_REQUIRE_GPIOLIB
725 select GENERIC_CLOCKEVENTS
730 select MULTI_IRQ_HANDLER
731 select ARM_CPU_SUSPEND if PM
734 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
739 select GENERIC_CLOCKEVENTS
740 select ARCH_REQUIRE_GPIOLIB
743 Support for Qualcomm MSM/QSD based systems. This runs on the
744 apps processor of the MSM/QSD and depends on a shared memory
745 interface to the modem processor which runs the baseband
746 stack and controls some vital subsystems
747 (clock and power control, etc).
750 bool "Renesas SH-Mobile / R-Mobile"
753 select HAVE_MACH_CLKDEV
755 select GENERIC_CLOCKEVENTS
756 select MIGHT_HAVE_CACHE_L2X0
759 select MULTI_IRQ_HANDLER
760 select PM_GENERIC_DOMAINS if PM
761 select NEED_MACH_MEMORY_H
763 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
769 select ARCH_MAY_HAVE_PC_FDC
770 select HAVE_PATA_PLATFORM
773 select ARCH_SPARSEMEM_ENABLE
774 select ARCH_USES_GETTIMEOFFSET
776 select NEED_MACH_IO_H
777 select NEED_MACH_MEMORY_H
779 On the Acorn Risc-PC, Linux can support the internal IDE disk and
780 CD-ROM interface, serial and parallel port, and the floppy drive.
787 select ARCH_SPARSEMEM_ENABLE
789 select ARCH_HAS_CPUFREQ
791 select GENERIC_CLOCKEVENTS
793 select ARCH_REQUIRE_GPIOLIB
795 select NEED_MACH_MEMORY_H
798 Support for StrongARM 11x0 based boards.
801 bool "Samsung S3C24XX SoCs"
803 select ARCH_HAS_CPUFREQ
806 select ARCH_USES_GETTIMEOFFSET
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C_RTC if RTC_CLASS
809 select HAVE_S3C2410_WATCHDOG if WATCHDOG
810 select NEED_MACH_IO_H
812 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
813 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
814 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
815 Samsung SMDK2410 development board (and derivatives).
818 bool "Samsung S3C64XX"
826 select ARCH_USES_GETTIMEOFFSET
827 select ARCH_HAS_CPUFREQ
828 select ARCH_REQUIRE_GPIOLIB
829 select SAMSUNG_CLKSRC
830 select SAMSUNG_IRQ_VIC_TIMER
831 select S3C_GPIO_TRACK
833 select USB_ARCH_HAS_OHCI
834 select SAMSUNG_GPIOLIB_4BIT
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C2410_WATCHDOG if WATCHDOG
838 Samsung S3C64XX series based systems
841 bool "Samsung S5P6440 S5P6450"
847 select HAVE_S3C2410_WATCHDOG if WATCHDOG
848 select GENERIC_CLOCKEVENTS
849 select HAVE_S3C2410_I2C if I2C
850 select HAVE_S3C_RTC if RTC_CLASS
852 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
856 bool "Samsung S5PC100"
861 select ARCH_USES_GETTIMEOFFSET
862 select HAVE_S3C2410_I2C if I2C
863 select HAVE_S3C_RTC if RTC_CLASS
864 select HAVE_S3C2410_WATCHDOG if WATCHDOG
866 Samsung S5PC100 series based systems
869 bool "Samsung S5PV210/S5PC110"
871 select ARCH_SPARSEMEM_ENABLE
872 select ARCH_HAS_HOLES_MEMORYMODEL
877 select ARCH_HAS_CPUFREQ
878 select GENERIC_CLOCKEVENTS
879 select HAVE_S3C2410_I2C if I2C
880 select HAVE_S3C_RTC if RTC_CLASS
881 select HAVE_S3C2410_WATCHDOG if WATCHDOG
882 select NEED_MACH_MEMORY_H
884 Samsung S5PV210/S5PC110 series based systems
887 bool "SAMSUNG EXYNOS"
889 select ARCH_SPARSEMEM_ENABLE
890 select ARCH_HAS_HOLES_MEMORYMODEL
894 select ARCH_HAS_CPUFREQ
895 select GENERIC_CLOCKEVENTS
896 select HAVE_S3C_RTC if RTC_CLASS
897 select HAVE_S3C2410_I2C if I2C
898 select HAVE_S3C2410_WATCHDOG if WATCHDOG
899 select NEED_MACH_MEMORY_H
901 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
910 select ARCH_USES_GETTIMEOFFSET
911 select NEED_MACH_MEMORY_H
912 select NEED_MACH_IO_H
914 Support for the StrongARM based Digital DNARD machine, also known
915 as "Shark" (<http://www.shark-linux.de/shark.html>).
918 bool "ST-Ericsson U300 Series"
924 select ARM_PATCH_PHYS_VIRT
926 select GENERIC_CLOCKEVENTS
928 select HAVE_MACH_CLKDEV
930 select ARCH_REQUIRE_GPIOLIB
932 Support for ST-Ericsson U300 series mobile platforms.
935 bool "ST-Ericsson U8500 Series"
939 select GENERIC_CLOCKEVENTS
941 select ARCH_REQUIRE_GPIOLIB
942 select ARCH_HAS_CPUFREQ
944 select MIGHT_HAVE_CACHE_L2X0
946 Support for ST-Ericsson's Ux500 architecture
949 bool "STMicroelectronics Nomadik"
954 select GENERIC_CLOCKEVENTS
956 select MIGHT_HAVE_CACHE_L2X0
957 select ARCH_REQUIRE_GPIOLIB
959 Support for the Nomadik platform by ST-Ericsson
963 select GENERIC_CLOCKEVENTS
964 select ARCH_REQUIRE_GPIOLIB
968 select GENERIC_ALLOCATOR
969 select GENERIC_IRQ_CHIP
970 select ARCH_HAS_HOLES_MEMORYMODEL
972 Support for TI's DaVinci platform.
978 select ARCH_REQUIRE_GPIOLIB
979 select ARCH_HAS_CPUFREQ
981 select GENERIC_CLOCKEVENTS
982 select ARCH_HAS_HOLES_MEMORYMODEL
984 Support for TI's OMAP platform (OMAP1/2/3/4).
989 select ARCH_REQUIRE_GPIOLIB
993 select GENERIC_CLOCKEVENTS
996 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
999 bool "VIA/WonderMedia 85xx"
1002 select ARCH_HAS_CPUFREQ
1003 select GENERIC_CLOCKEVENTS
1004 select ARCH_REQUIRE_GPIOLIB
1007 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1010 bool "Xilinx Zynq ARM Cortex A9 Platform"
1012 select GENERIC_CLOCKEVENTS
1013 select CLKDEV_LOOKUP
1017 select MIGHT_HAVE_CACHE_L2X0
1020 Support for Xilinx Zynq ARM Cortex A9 Platform
1024 # This is sorted alphabetically by mach-* pathname. However, plat-*
1025 # Kconfigs may be included either alphabetically (according to the
1026 # plat- suffix) or along side the corresponding mach-* source.
1028 source "arch/arm/mach-mvebu/Kconfig"
1030 source "arch/arm/mach-at91/Kconfig"
1032 source "arch/arm/mach-bcmring/Kconfig"
1034 source "arch/arm/mach-clps711x/Kconfig"
1036 source "arch/arm/mach-cns3xxx/Kconfig"
1038 source "arch/arm/mach-davinci/Kconfig"
1040 source "arch/arm/mach-dove/Kconfig"
1042 source "arch/arm/mach-ep93xx/Kconfig"
1044 source "arch/arm/mach-footbridge/Kconfig"
1046 source "arch/arm/mach-gemini/Kconfig"
1048 source "arch/arm/mach-h720x/Kconfig"
1050 source "arch/arm/mach-integrator/Kconfig"
1052 source "arch/arm/mach-iop32x/Kconfig"
1054 source "arch/arm/mach-iop33x/Kconfig"
1056 source "arch/arm/mach-iop13xx/Kconfig"
1058 source "arch/arm/mach-ixp4xx/Kconfig"
1060 source "arch/arm/mach-kirkwood/Kconfig"
1062 source "arch/arm/mach-ks8695/Kconfig"
1064 source "arch/arm/mach-msm/Kconfig"
1066 source "arch/arm/mach-mv78xx0/Kconfig"
1068 source "arch/arm/plat-mxc/Kconfig"
1070 source "arch/arm/mach-mxs/Kconfig"
1072 source "arch/arm/mach-netx/Kconfig"
1074 source "arch/arm/mach-nomadik/Kconfig"
1075 source "arch/arm/plat-nomadik/Kconfig"
1077 source "arch/arm/plat-omap/Kconfig"
1079 source "arch/arm/mach-omap1/Kconfig"
1081 source "arch/arm/mach-omap2/Kconfig"
1083 source "arch/arm/mach-orion5x/Kconfig"
1085 source "arch/arm/mach-pxa/Kconfig"
1086 source "arch/arm/plat-pxa/Kconfig"
1088 source "arch/arm/mach-mmp/Kconfig"
1090 source "arch/arm/mach-realview/Kconfig"
1092 source "arch/arm/mach-sa1100/Kconfig"
1094 source "arch/arm/plat-samsung/Kconfig"
1095 source "arch/arm/plat-s3c24xx/Kconfig"
1097 source "arch/arm/plat-spear/Kconfig"
1099 source "arch/arm/mach-s3c24xx/Kconfig"
1101 source "arch/arm/mach-s3c2412/Kconfig"
1102 source "arch/arm/mach-s3c2440/Kconfig"
1106 source "arch/arm/mach-s3c64xx/Kconfig"
1109 source "arch/arm/mach-s5p64x0/Kconfig"
1111 source "arch/arm/mach-s5pc100/Kconfig"
1113 source "arch/arm/mach-s5pv210/Kconfig"
1115 source "arch/arm/mach-exynos/Kconfig"
1117 source "arch/arm/mach-shmobile/Kconfig"
1119 source "arch/arm/mach-tegra/Kconfig"
1121 source "arch/arm/mach-u300/Kconfig"
1123 source "arch/arm/mach-ux500/Kconfig"
1125 source "arch/arm/mach-versatile/Kconfig"
1127 source "arch/arm/mach-vexpress/Kconfig"
1128 source "arch/arm/plat-versatile/Kconfig"
1130 source "arch/arm/mach-vt8500/Kconfig"
1132 source "arch/arm/mach-w90x900/Kconfig"
1134 # Definitions to make life easier
1140 select GENERIC_CLOCKEVENTS
1145 select GENERIC_IRQ_CHIP
1151 config PLAT_VERSATILE
1154 config ARM_TIMER_SP804
1157 select HAVE_SCHED_CLOCK
1159 source arch/arm/mm/Kconfig
1163 default 16 if ARCH_EP93XX
1167 bool "Enable iWMMXt support"
1168 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1169 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1171 Enable support for iWMMXt context switching at run time if
1172 running on a CPU that supports it.
1176 depends on CPU_XSCALE
1180 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1181 (!ARCH_OMAP3 || OMAP3_EMU)
1185 config MULTI_IRQ_HANDLER
1188 Allow each machine to specify it's own IRQ handler at run time.
1191 source "arch/arm/Kconfig-nommu"
1194 config ARM_ERRATA_326103
1195 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1198 Executing a SWP instruction to read-only memory does not set bit 11
1199 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1200 treat the access as a read, preventing a COW from occurring and
1201 causing the faulting task to livelock.
1203 config ARM_ERRATA_411920
1204 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1205 depends on CPU_V6 || CPU_V6K
1207 Invalidation of the Instruction Cache operation can
1208 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1209 It does not affect the MPCore. This option enables the ARM Ltd.
1210 recommended workaround.
1212 config ARM_ERRATA_430973
1213 bool "ARM errata: Stale prediction on replaced interworking branch"
1216 This option enables the workaround for the 430973 Cortex-A8
1217 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1218 interworking branch is replaced with another code sequence at the
1219 same virtual address, whether due to self-modifying code or virtual
1220 to physical address re-mapping, Cortex-A8 does not recover from the
1221 stale interworking branch prediction. This results in Cortex-A8
1222 executing the new code sequence in the incorrect ARM or Thumb state.
1223 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1224 and also flushes the branch target cache at every context switch.
1225 Note that setting specific bits in the ACTLR register may not be
1226 available in non-secure mode.
1228 config ARM_ERRATA_458693
1229 bool "ARM errata: Processor deadlock when a false hazard is created"
1232 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1233 erratum. For very specific sequences of memory operations, it is
1234 possible for a hazard condition intended for a cache line to instead
1235 be incorrectly associated with a different cache line. This false
1236 hazard might then cause a processor deadlock. The workaround enables
1237 the L1 caching of the NEON accesses and disables the PLD instruction
1238 in the ACTLR register. Note that setting specific bits in the ACTLR
1239 register may not be available in non-secure mode.
1241 config ARM_ERRATA_460075
1242 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1245 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1246 erratum. Any asynchronous access to the L2 cache may encounter a
1247 situation in which recent store transactions to the L2 cache are lost
1248 and overwritten with stale memory contents from external memory. The
1249 workaround disables the write-allocate mode for the L2 cache via the
1250 ACTLR register. Note that setting specific bits in the ACTLR register
1251 may not be available in non-secure mode.
1253 config ARM_ERRATA_742230
1254 bool "ARM errata: DMB operation may be faulty"
1255 depends on CPU_V7 && SMP
1257 This option enables the workaround for the 742230 Cortex-A9
1258 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1259 between two write operations may not ensure the correct visibility
1260 ordering of the two writes. This workaround sets a specific bit in
1261 the diagnostic register of the Cortex-A9 which causes the DMB
1262 instruction to behave as a DSB, ensuring the correct behaviour of
1265 config ARM_ERRATA_742231
1266 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1267 depends on CPU_V7 && SMP
1269 This option enables the workaround for the 742231 Cortex-A9
1270 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1271 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1272 accessing some data located in the same cache line, may get corrupted
1273 data due to bad handling of the address hazard when the line gets
1274 replaced from one of the CPUs at the same time as another CPU is
1275 accessing it. This workaround sets specific bits in the diagnostic
1276 register of the Cortex-A9 which reduces the linefill issuing
1277 capabilities of the processor.
1279 config PL310_ERRATA_588369
1280 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1281 depends on CACHE_L2X0
1283 The PL310 L2 cache controller implements three types of Clean &
1284 Invalidate maintenance operations: by Physical Address
1285 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1286 They are architecturally defined to behave as the execution of a
1287 clean operation followed immediately by an invalidate operation,
1288 both performing to the same memory location. This functionality
1289 is not correctly implemented in PL310 as clean lines are not
1290 invalidated as a result of these operations.
1292 config ARM_ERRATA_720789
1293 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1296 This option enables the workaround for the 720789 Cortex-A9 (prior to
1297 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1298 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1299 As a consequence of this erratum, some TLB entries which should be
1300 invalidated are not, resulting in an incoherency in the system page
1301 tables. The workaround changes the TLB flushing routines to invalidate
1302 entries regardless of the ASID.
1304 config PL310_ERRATA_727915
1305 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1306 depends on CACHE_L2X0
1308 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1309 operation (offset 0x7FC). This operation runs in background so that
1310 PL310 can handle normal accesses while it is in progress. Under very
1311 rare circumstances, due to this erratum, write data can be lost when
1312 PL310 treats a cacheable write transaction during a Clean &
1313 Invalidate by Way operation.
1315 config ARM_ERRATA_743622
1316 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1319 This option enables the workaround for the 743622 Cortex-A9
1320 (r2p*) erratum. Under very rare conditions, a faulty
1321 optimisation in the Cortex-A9 Store Buffer may lead to data
1322 corruption. This workaround sets a specific bit in the diagnostic
1323 register of the Cortex-A9 which disables the Store Buffer
1324 optimisation, preventing the defect from occurring. This has no
1325 visible impact on the overall performance or power consumption of the
1328 config ARM_ERRATA_751472
1329 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1332 This option enables the workaround for the 751472 Cortex-A9 (prior
1333 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1334 completion of a following broadcasted operation if the second
1335 operation is received by a CPU before the ICIALLUIS has completed,
1336 potentially leading to corrupted entries in the cache or TLB.
1338 config PL310_ERRATA_753970
1339 bool "PL310 errata: cache sync operation may be faulty"
1340 depends on CACHE_PL310
1342 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1344 Under some condition the effect of cache sync operation on
1345 the store buffer still remains when the operation completes.
1346 This means that the store buffer is always asked to drain and
1347 this prevents it from merging any further writes. The workaround
1348 is to replace the normal offset of cache sync operation (0x730)
1349 by another offset targeting an unmapped PL310 register 0x740.
1350 This has the same effect as the cache sync operation: store buffer
1351 drain and waiting for all buffers empty.
1353 config ARM_ERRATA_754322
1354 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1357 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1358 r3p*) erratum. A speculative memory access may cause a page table walk
1359 which starts prior to an ASID switch but completes afterwards. This
1360 can populate the micro-TLB with a stale entry which may be hit with
1361 the new ASID. This workaround places two dsb instructions in the mm
1362 switching code so that no page table walks can cross the ASID switch.
1364 config ARM_ERRATA_754327
1365 bool "ARM errata: no automatic Store Buffer drain"
1366 depends on CPU_V7 && SMP
1368 This option enables the workaround for the 754327 Cortex-A9 (prior to
1369 r2p0) erratum. The Store Buffer does not have any automatic draining
1370 mechanism and therefore a livelock may occur if an external agent
1371 continuously polls a memory location waiting to observe an update.
1372 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1373 written polling loops from denying visibility of updates to memory.
1375 config ARM_ERRATA_364296
1376 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1377 depends on CPU_V6 && !SMP
1379 This options enables the workaround for the 364296 ARM1136
1380 r0p2 erratum (possible cache data corruption with
1381 hit-under-miss enabled). It sets the undocumented bit 31 in
1382 the auxiliary control register and the FI bit in the control
1383 register, thus disabling hit-under-miss without putting the
1384 processor into full low interrupt latency mode. ARM11MPCore
1387 config ARM_ERRATA_764369
1388 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1389 depends on CPU_V7 && SMP
1391 This option enables the workaround for erratum 764369
1392 affecting Cortex-A9 MPCore with two or more processors (all
1393 current revisions). Under certain timing circumstances, a data
1394 cache line maintenance operation by MVA targeting an Inner
1395 Shareable memory region may fail to proceed up to either the
1396 Point of Coherency or to the Point of Unification of the
1397 system. This workaround adds a DSB instruction before the
1398 relevant cache maintenance functions and sets a specific bit
1399 in the diagnostic control register of the SCU.
1401 config PL310_ERRATA_769419
1402 bool "PL310 errata: no automatic Store Buffer drain"
1403 depends on CACHE_L2X0
1405 On revisions of the PL310 prior to r3p2, the Store Buffer does
1406 not automatically drain. This can cause normal, non-cacheable
1407 writes to be retained when the memory system is idle, leading
1408 to suboptimal I/O performance for drivers using coherent DMA.
1409 This option adds a write barrier to the cpu_idle loop so that,
1410 on systems with an outer cache, the store buffer is drained
1415 source "arch/arm/common/Kconfig"
1425 Find out whether you have ISA slots on your motherboard. ISA is the
1426 name of a bus system, i.e. the way the CPU talks to the other stuff
1427 inside your box. Other bus systems are PCI, EISA, MicroChannel
1428 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1429 newer boards don't support it. If you have ISA, say Y, otherwise N.
1431 # Select ISA DMA controller support
1436 # Select ISA DMA interface
1441 bool "PCI support" if MIGHT_HAVE_PCI
1443 Find out whether you have a PCI motherboard. PCI is the name of a
1444 bus system, i.e. the way the CPU talks to the other stuff inside
1445 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1446 VESA. If you have PCI, say Y, otherwise N.
1452 config PCI_NANOENGINE
1453 bool "BSE nanoEngine PCI support"
1454 depends on SA1100_NANOENGINE
1456 Enable PCI on the BSE nanoEngine board.
1461 # Select the host bridge type
1462 config PCI_HOST_VIA82C505
1464 depends on PCI && ARCH_SHARK
1467 config PCI_HOST_ITE8152
1469 depends on PCI && MACH_ARMCORE
1473 source "drivers/pci/Kconfig"
1475 source "drivers/pcmcia/Kconfig"
1479 menu "Kernel Features"
1484 This option should be selected by machines which have an SMP-
1487 The only effect of this option is to make the SMP-related
1488 options available to the user for configuration.
1491 bool "Symmetric Multi-Processing"
1492 depends on CPU_V6K || CPU_V7
1493 depends on GENERIC_CLOCKEVENTS
1496 select USE_GENERIC_SMP_HELPERS
1497 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1499 This enables support for systems with more than one CPU. If you have
1500 a system with only one CPU, like most personal computers, say N. If
1501 you have a system with more than one CPU, say Y.
1503 If you say N here, the kernel will run on single and multiprocessor
1504 machines, but will use only one CPU of a multiprocessor machine. If
1505 you say Y here, the kernel will run on many, but not all, single
1506 processor machines. On a single processor machine, the kernel will
1507 run faster if you say N here.
1509 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1510 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1511 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1513 If you don't know what to do here, say N.
1516 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1517 depends on EXPERIMENTAL
1518 depends on SMP && !XIP_KERNEL
1521 SMP kernels contain instructions which fail on non-SMP processors.
1522 Enabling this option allows the kernel to modify itself to make
1523 these instructions safe. Disabling it allows about 1K of space
1526 If you don't know what to do here, say Y.
1528 config ARM_CPU_TOPOLOGY
1529 bool "Support cpu topology definition"
1530 depends on SMP && CPU_V7
1533 Support ARM cpu topology definition. The MPIDR register defines
1534 affinity between processors which is then used to describe the cpu
1535 topology of an ARM System.
1538 bool "Multi-core scheduler support"
1539 depends on ARM_CPU_TOPOLOGY
1541 Multi-core scheduler support improves the CPU scheduler's decision
1542 making when dealing with multi-core CPU chips at a cost of slightly
1543 increased overhead in some places. If unsure say N here.
1546 bool "SMT scheduler support"
1547 depends on ARM_CPU_TOPOLOGY
1549 Improves the CPU scheduler's decision making when dealing with
1550 MultiThreading at a cost of slightly increased overhead in some
1551 places. If unsure say N here.
1556 This option enables support for the ARM system coherency unit
1558 config ARM_ARCH_TIMER
1559 bool "Architected timer support"
1562 This option enables support for the ARM architected timer
1568 This options enables support for the ARM timer and watchdog unit
1571 prompt "Memory split"
1574 Select the desired split between kernel and user memory.
1576 If you are not absolutely sure what you are doing, leave this
1580 bool "3G/1G user/kernel split"
1582 bool "2G/2G user/kernel split"
1584 bool "1G/3G user/kernel split"
1589 default 0x40000000 if VMSPLIT_1G
1590 default 0x80000000 if VMSPLIT_2G
1594 int "Maximum number of CPUs (2-32)"
1600 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1601 depends on SMP && HOTPLUG && EXPERIMENTAL
1603 Say Y here to experiment with turning CPUs off and on. CPUs
1604 can be controlled through /sys/devices/system/cpu.
1607 bool "Use local timer interrupts"
1610 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1612 Enable support for local timers on SMP platforms, rather then the
1613 legacy IPI broadcast method. Local timers allows the system
1614 accounting to be spread across the timer interval, preventing a
1615 "thundering herd" at every timer tick.
1619 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1620 default 355 if ARCH_U8500
1621 default 264 if MACH_H4700
1622 default 512 if SOC_OMAP5
1625 Maximum number of GPIOs in the system.
1627 If unsure, leave the default value.
1629 source kernel/Kconfig.preempt
1633 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1634 ARCH_S5PV210 || ARCH_EXYNOS4
1635 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1636 default AT91_TIMER_HZ if ARCH_AT91
1637 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1640 config THUMB2_KERNEL
1641 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1642 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1644 select ARM_ASM_UNIFIED
1647 By enabling this option, the kernel will be compiled in
1648 Thumb-2 mode. A compiler/assembler that understand the unified
1649 ARM-Thumb syntax is needed.
1653 config THUMB2_AVOID_R_ARM_THM_JUMP11
1654 bool "Work around buggy Thumb-2 short branch relocations in gas"
1655 depends on THUMB2_KERNEL && MODULES
1658 Various binutils versions can resolve Thumb-2 branches to
1659 locally-defined, preemptible global symbols as short-range "b.n"
1660 branch instructions.
1662 This is a problem, because there's no guarantee the final
1663 destination of the symbol, or any candidate locations for a
1664 trampoline, are within range of the branch. For this reason, the
1665 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1666 relocation in modules at all, and it makes little sense to add
1669 The symptom is that the kernel fails with an "unsupported
1670 relocation" error when loading some modules.
1672 Until fixed tools are available, passing
1673 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1674 code which hits this problem, at the cost of a bit of extra runtime
1675 stack usage in some cases.
1677 The problem is described in more detail at:
1678 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1680 Only Thumb-2 kernels are affected.
1682 Unless you are sure your tools don't have this problem, say Y.
1684 config ARM_ASM_UNIFIED
1688 bool "Use the ARM EABI to compile the kernel"
1690 This option allows for the kernel to be compiled using the latest
1691 ARM ABI (aka EABI). This is only useful if you are using a user
1692 space environment that is also compiled with EABI.
1694 Since there are major incompatibilities between the legacy ABI and
1695 EABI, especially with regard to structure member alignment, this
1696 option also changes the kernel syscall calling convention to
1697 disambiguate both ABIs and allow for backward compatibility support
1698 (selected with CONFIG_OABI_COMPAT).
1700 To use this you need GCC version 4.0.0 or later.
1703 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1704 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1707 This option preserves the old syscall interface along with the
1708 new (ARM EABI) one. It also provides a compatibility layer to
1709 intercept syscalls that have structure arguments which layout
1710 in memory differs between the legacy ABI and the new ARM EABI
1711 (only for non "thumb" binaries). This option adds a tiny
1712 overhead to all syscalls and produces a slightly larger kernel.
1713 If you know you'll be using only pure EABI user space then you
1714 can say N here. If this option is not selected and you attempt
1715 to execute a legacy ABI binary then the result will be
1716 UNPREDICTABLE (in fact it can be predicted that it won't work
1717 at all). If in doubt say Y.
1719 config ARCH_HAS_HOLES_MEMORYMODEL
1722 config ARCH_SPARSEMEM_ENABLE
1725 config ARCH_SPARSEMEM_DEFAULT
1726 def_bool ARCH_SPARSEMEM_ENABLE
1728 config ARCH_SELECT_MEMORY_MODEL
1729 def_bool ARCH_SPARSEMEM_ENABLE
1731 config HAVE_ARCH_PFN_VALID
1732 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1735 bool "High Memory Support"
1738 The address space of ARM processors is only 4 Gigabytes large
1739 and it has to accommodate user address space, kernel address
1740 space as well as some memory mapped IO. That means that, if you
1741 have a large amount of physical memory and/or IO, not all of the
1742 memory can be "permanently mapped" by the kernel. The physical
1743 memory that is not permanently mapped is called "high memory".
1745 Depending on the selected kernel/user memory split, minimum
1746 vmalloc space and actual amount of RAM, you may not need this
1747 option which should result in a slightly faster kernel.
1752 bool "Allocate 2nd-level pagetables from highmem"
1755 config HW_PERF_EVENTS
1756 bool "Enable hardware performance counter support for perf events"
1757 depends on PERF_EVENTS && CPU_HAS_PMU
1760 Enable hardware performance counter support for perf events. If
1761 disabled, perf events will use software events only.
1765 config FORCE_MAX_ZONEORDER
1766 int "Maximum zone order" if ARCH_SHMOBILE
1767 range 11 64 if ARCH_SHMOBILE
1768 default "9" if SA1111
1771 The kernel memory allocator divides physically contiguous memory
1772 blocks into "zones", where each zone is a power of two number of
1773 pages. This option selects the largest power of two that the kernel
1774 keeps in the memory allocator. If you need to allocate very large
1775 blocks of physically contiguous memory, then you may need to
1776 increase this value.
1778 This config option is actually maximum order plus one. For example,
1779 a value of 11 means that the largest free memory block is 2^10 pages.
1782 bool "Timer and CPU usage LEDs"
1783 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1784 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1785 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1786 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1787 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1788 ARCH_AT91 || ARCH_DAVINCI || \
1789 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1791 If you say Y here, the LEDs on your machine will be used
1792 to provide useful information about your current system status.
1794 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1795 be able to select which LEDs are active using the options below. If
1796 you are compiling a kernel for the EBSA-110 or the LART however, the
1797 red LED will simply flash regularly to indicate that the system is
1798 still functional. It is safe to say Y here if you have a CATS
1799 system, but the driver will do nothing.
1802 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1803 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1804 || MACH_OMAP_PERSEUS2
1806 depends on !GENERIC_CLOCKEVENTS
1807 default y if ARCH_EBSA110
1809 If you say Y here, one of the system LEDs (the green one on the
1810 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1811 will flash regularly to indicate that the system is still
1812 operational. This is mainly useful to kernel hackers who are
1813 debugging unstable kernels.
1815 The LART uses the same LED for both Timer LED and CPU usage LED
1816 functions. You may choose to use both, but the Timer LED function
1817 will overrule the CPU usage LED.
1820 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1822 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1823 || MACH_OMAP_PERSEUS2
1826 If you say Y here, the red LED will be used to give a good real
1827 time indication of CPU usage, by lighting whenever the idle task
1828 is not currently executing.
1830 The LART uses the same LED for both Timer LED and CPU usage LED
1831 functions. You may choose to use both, but the Timer LED function
1832 will overrule the CPU usage LED.
1834 config ALIGNMENT_TRAP
1836 depends on CPU_CP15_MMU
1837 default y if !ARCH_EBSA110
1838 select HAVE_PROC_CPU if PROC_FS
1840 ARM processors cannot fetch/store information which is not
1841 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1842 address divisible by 4. On 32-bit ARM processors, these non-aligned
1843 fetch/store instructions will be emulated in software if you say
1844 here, which has a severe performance impact. This is necessary for
1845 correct operation of some network protocols. With an IP-only
1846 configuration it is safe to say N, otherwise say Y.
1848 config UACCESS_WITH_MEMCPY
1849 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1850 depends on MMU && EXPERIMENTAL
1851 default y if CPU_FEROCEON
1853 Implement faster copy_to_user and clear_user methods for CPU
1854 cores where a 8-word STM instruction give significantly higher
1855 memory write throughput than a sequence of individual 32bit stores.
1857 A possible side effect is a slight increase in scheduling latency
1858 between threads sharing the same address space if they invoke
1859 such copy operations with large buffers.
1861 However, if the CPU data cache is using a write-allocate mode,
1862 this option is unlikely to provide any performance gain.
1866 prompt "Enable seccomp to safely compute untrusted bytecode"
1868 This kernel feature is useful for number crunching applications
1869 that may need to compute untrusted bytecode during their
1870 execution. By using pipes or other transports made available to
1871 the process as file descriptors supporting the read/write
1872 syscalls, it's possible to isolate those applications in
1873 their own address space using seccomp. Once seccomp is
1874 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1875 and the task is only allowed to execute a few safe syscalls
1876 defined by each seccomp mode.
1878 config CC_STACKPROTECTOR
1879 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1880 depends on EXPERIMENTAL
1882 This option turns on the -fstack-protector GCC feature. This
1883 feature puts, at the beginning of functions, a canary value on
1884 the stack just before the return address, and validates
1885 the value just before actually returning. Stack based buffer
1886 overflows (that need to overwrite this return address) now also
1887 overwrite the canary, which gets detected and the attack is then
1888 neutralized via a kernel panic.
1889 This feature requires gcc version 4.2 or above.
1891 config DEPRECATED_PARAM_STRUCT
1892 bool "Provide old way to pass kernel parameters"
1894 This was deprecated in 2001 and announced to live on for 5 years.
1895 Some old boot loaders still use this way.
1902 bool "Flattened Device Tree support"
1904 select OF_EARLY_FLATTREE
1907 Include support for flattened device tree machine descriptions.
1909 # Compressed boot loader in ROM. Yes, we really want to ask about
1910 # TEXT and BSS so we preserve their values in the config files.
1911 config ZBOOT_ROM_TEXT
1912 hex "Compressed ROM boot loader base address"
1915 The physical address at which the ROM-able zImage is to be
1916 placed in the target. Platforms which normally make use of
1917 ROM-able zImage formats normally set this to a suitable
1918 value in their defconfig file.
1920 If ZBOOT_ROM is not enabled, this has no effect.
1922 config ZBOOT_ROM_BSS
1923 hex "Compressed ROM boot loader BSS address"
1926 The base address of an area of read/write memory in the target
1927 for the ROM-able zImage which must be available while the
1928 decompressor is running. It must be large enough to hold the
1929 entire decompressed kernel plus an additional 128 KiB.
1930 Platforms which normally make use of ROM-able zImage formats
1931 normally set this to a suitable value in their defconfig file.
1933 If ZBOOT_ROM is not enabled, this has no effect.
1936 bool "Compressed boot loader in ROM/flash"
1937 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1939 Say Y here if you intend to execute your compressed kernel image
1940 (zImage) directly from ROM or flash. If unsure, say N.
1943 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1944 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1945 default ZBOOT_ROM_NONE
1947 Include experimental SD/MMC loading code in the ROM-able zImage.
1948 With this enabled it is possible to write the ROM-able zImage
1949 kernel image to an MMC or SD card and boot the kernel straight
1950 from the reset vector. At reset the processor Mask ROM will load
1951 the first part of the ROM-able zImage which in turn loads the
1952 rest the kernel image to RAM.
1954 config ZBOOT_ROM_NONE
1955 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1957 Do not load image from SD or MMC
1959 config ZBOOT_ROM_MMCIF
1960 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1962 Load image from MMCIF hardware block.
1964 config ZBOOT_ROM_SH_MOBILE_SDHI
1965 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1967 Load image from SDHI hardware block
1971 config ARM_APPENDED_DTB
1972 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1973 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1975 With this option, the boot code will look for a device tree binary
1976 (DTB) appended to zImage
1977 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1979 This is meant as a backward compatibility convenience for those
1980 systems with a bootloader that can't be upgraded to accommodate
1981 the documented boot protocol using a device tree.
1983 Beware that there is very little in terms of protection against
1984 this option being confused by leftover garbage in memory that might
1985 look like a DTB header after a reboot if no actual DTB is appended
1986 to zImage. Do not leave this option active in a production kernel
1987 if you don't intend to always append a DTB. Proper passing of the
1988 location into r2 of a bootloader provided DTB is always preferable
1991 config ARM_ATAG_DTB_COMPAT
1992 bool "Supplement the appended DTB with traditional ATAG information"
1993 depends on ARM_APPENDED_DTB
1995 Some old bootloaders can't be updated to a DTB capable one, yet
1996 they provide ATAGs with memory configuration, the ramdisk address,
1997 the kernel cmdline string, etc. Such information is dynamically
1998 provided by the bootloader and can't always be stored in a static
1999 DTB. To allow a device tree enabled kernel to be used with such
2000 bootloaders, this option allows zImage to extract the information
2001 from the ATAG list and store it at run time into the appended DTB.
2004 string "Default kernel command string"
2007 On some architectures (EBSA110 and CATS), there is currently no way
2008 for the boot loader to pass arguments to the kernel. For these
2009 architectures, you should supply some command-line options at build
2010 time by entering them here. As a minimum, you should specify the
2011 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2014 prompt "Kernel command line type" if CMDLINE != ""
2015 default CMDLINE_FROM_BOOTLOADER
2017 config CMDLINE_FROM_BOOTLOADER
2018 bool "Use bootloader kernel arguments if available"
2020 Uses the command-line options passed by the boot loader. If
2021 the boot loader doesn't provide any, the default kernel command
2022 string provided in CMDLINE will be used.
2024 config CMDLINE_EXTEND
2025 bool "Extend bootloader kernel arguments"
2027 The command-line arguments provided by the boot loader will be
2028 appended to the default kernel command string.
2030 config CMDLINE_FORCE
2031 bool "Always use the default kernel command string"
2033 Always use the default kernel command string, even if the boot
2034 loader passes other arguments to the kernel.
2035 This is useful if you cannot or don't want to change the
2036 command-line options your boot loader passes to the kernel.
2040 bool "Kernel Execute-In-Place from ROM"
2041 depends on !ZBOOT_ROM && !ARM_LPAE
2043 Execute-In-Place allows the kernel to run from non-volatile storage
2044 directly addressable by the CPU, such as NOR flash. This saves RAM
2045 space since the text section of the kernel is not loaded from flash
2046 to RAM. Read-write sections, such as the data section and stack,
2047 are still copied to RAM. The XIP kernel is not compressed since
2048 it has to run directly from flash, so it will take more space to
2049 store it. The flash address used to link the kernel object files,
2050 and for storing it, is configuration dependent. Therefore, if you
2051 say Y here, you must know the proper physical address where to
2052 store the kernel image depending on your own flash memory usage.
2054 Also note that the make target becomes "make xipImage" rather than
2055 "make zImage" or "make Image". The final kernel binary to put in
2056 ROM memory will be arch/arm/boot/xipImage.
2060 config XIP_PHYS_ADDR
2061 hex "XIP Kernel Physical Location"
2062 depends on XIP_KERNEL
2063 default "0x00080000"
2065 This is the physical address in your flash memory the kernel will
2066 be linked for and stored to. This address is dependent on your
2070 bool "Kexec system call (EXPERIMENTAL)"
2071 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2073 kexec is a system call that implements the ability to shutdown your
2074 current kernel, and to start another kernel. It is like a reboot
2075 but it is independent of the system firmware. And like a reboot
2076 you can start any kernel with it, not just Linux.
2078 It is an ongoing process to be certain the hardware in a machine
2079 is properly shutdown, so do not be surprised if this code does not
2080 initially work for you. It may help to enable device hotplugging
2084 bool "Export atags in procfs"
2088 Should the atags used to boot the kernel be exported in an "atags"
2089 file in procfs. Useful with kexec.
2092 bool "Build kdump crash kernel (EXPERIMENTAL)"
2093 depends on EXPERIMENTAL
2095 Generate crash dump after being started by kexec. This should
2096 be normally only set in special crash dump kernels which are
2097 loaded in the main kernel with kexec-tools into a specially
2098 reserved region and then later executed after a crash by
2099 kdump/kexec. The crash dump kernel must be compiled to a
2100 memory address not used by the main kernel
2102 For more details see Documentation/kdump/kdump.txt
2104 config AUTO_ZRELADDR
2105 bool "Auto calculation of the decompressed kernel image address"
2106 depends on !ZBOOT_ROM && !ARCH_U300
2108 ZRELADDR is the physical address where the decompressed kernel
2109 image will be placed. If AUTO_ZRELADDR is selected, the address
2110 will be determined at run-time by masking the current IP with
2111 0xf8000000. This assumes the zImage being placed in the first 128MB
2112 from start of memory.
2116 menu "CPU Power Management"
2120 source "drivers/cpufreq/Kconfig"
2123 tristate "CPUfreq driver for i.MX CPUs"
2124 depends on ARCH_MXC && CPU_FREQ
2126 This enables the CPUfreq driver for i.MX CPUs.
2128 config CPU_FREQ_SA1100
2131 config CPU_FREQ_SA1110
2134 config CPU_FREQ_INTEGRATOR
2135 tristate "CPUfreq driver for ARM Integrator CPUs"
2136 depends on ARCH_INTEGRATOR && CPU_FREQ
2139 This enables the CPUfreq driver for ARM Integrator CPUs.
2141 For details, take a look at <file:Documentation/cpu-freq>.
2147 depends on CPU_FREQ && ARCH_PXA && PXA25x
2149 select CPU_FREQ_TABLE
2150 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2155 Internal configuration node for common cpufreq on Samsung SoC
2157 config CPU_FREQ_S3C24XX
2158 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2159 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2162 This enables the CPUfreq driver for the Samsung S3C24XX family
2165 For details, take a look at <file:Documentation/cpu-freq>.
2169 config CPU_FREQ_S3C24XX_PLL
2170 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2171 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2173 Compile in support for changing the PLL frequency from the
2174 S3C24XX series CPUfreq driver. The PLL takes time to settle
2175 after a frequency change, so by default it is not enabled.
2177 This also means that the PLL tables for the selected CPU(s) will
2178 be built which may increase the size of the kernel image.
2180 config CPU_FREQ_S3C24XX_DEBUG
2181 bool "Debug CPUfreq Samsung driver core"
2182 depends on CPU_FREQ_S3C24XX
2184 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2186 config CPU_FREQ_S3C24XX_IODEBUG
2187 bool "Debug CPUfreq Samsung driver IO timing"
2188 depends on CPU_FREQ_S3C24XX
2190 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2192 config CPU_FREQ_S3C24XX_DEBUGFS
2193 bool "Export debugfs for CPUFreq"
2194 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2196 Export status information via debugfs.
2200 source "drivers/cpuidle/Kconfig"
2204 menu "Floating point emulation"
2206 comment "At least one emulation must be selected"
2209 bool "NWFPE math emulation"
2210 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2212 Say Y to include the NWFPE floating point emulator in the kernel.
2213 This is necessary to run most binaries. Linux does not currently
2214 support floating point hardware so you need to say Y here even if
2215 your machine has an FPA or floating point co-processor podule.
2217 You may say N here if you are going to load the Acorn FPEmulator
2218 early in the bootup.
2221 bool "Support extended precision"
2222 depends on FPE_NWFPE
2224 Say Y to include 80-bit support in the kernel floating-point
2225 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2226 Note that gcc does not generate 80-bit operations by default,
2227 so in most cases this option only enlarges the size of the
2228 floating point emulator without any good reason.
2230 You almost surely want to say N here.
2233 bool "FastFPE math emulation (EXPERIMENTAL)"
2234 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2236 Say Y here to include the FAST floating point emulator in the kernel.
2237 This is an experimental much faster emulator which now also has full
2238 precision for the mantissa. It does not support any exceptions.
2239 It is very simple, and approximately 3-6 times faster than NWFPE.
2241 It should be sufficient for most programs. It may be not suitable
2242 for scientific calculations, but you have to check this for yourself.
2243 If you do not feel you need a faster FP emulation you should better
2247 bool "VFP-format floating point maths"
2248 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2250 Say Y to include VFP support code in the kernel. This is needed
2251 if your hardware includes a VFP unit.
2253 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2254 release notes and additional status information.
2256 Say N if your target does not have VFP hardware.
2264 bool "Advanced SIMD (NEON) Extension support"
2265 depends on VFPv3 && CPU_V7
2267 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2272 menu "Userspace binary formats"
2274 source "fs/Kconfig.binfmt"
2277 tristate "RISC OS personality"
2280 Say Y here to include the kernel code necessary if you want to run
2281 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2282 experimental; if this sounds frightening, say N and sleep in peace.
2283 You can also say M here to compile this support as a module (which
2284 will be called arthur).
2288 menu "Power management options"
2290 source "kernel/power/Kconfig"
2292 config ARCH_SUSPEND_POSSIBLE
2293 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2294 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2295 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2298 config ARM_CPU_SUSPEND
2303 source "net/Kconfig"
2305 source "drivers/Kconfig"
2309 source "arch/arm/Kconfig.debug"
2311 source "security/Kconfig"
2313 source "crypto/Kconfig"
2315 source "lib/Kconfig"