4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
256 select ARCH_HAS_CPUFREQ
258 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_IO_H
265 select NEED_MACH_MEMORY_H
267 select MULTI_IRQ_HANDLER
269 Support for ARM's Integrator platform.
272 bool "ARM Ltd. RealView family"
275 select HAVE_MACH_CLKDEV
277 select GENERIC_CLOCKEVENTS
278 select ARCH_WANT_OPTIONAL_GPIOLIB
279 select PLAT_VERSATILE
280 select PLAT_VERSATILE_CLCD
281 select ARM_TIMER_SP804
282 select GPIO_PL061 if GPIOLIB
283 select NEED_MACH_MEMORY_H
285 This enables support for ARM Ltd RealView boards.
287 config ARCH_VERSATILE
288 bool "ARM Ltd. Versatile family"
292 select HAVE_MACH_CLKDEV
294 select GENERIC_CLOCKEVENTS
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select PLAT_VERSATILE
297 select PLAT_VERSATILE_CLCD
298 select PLAT_VERSATILE_FPGA_IRQ
299 select ARM_TIMER_SP804
301 This enables support for ARM Ltd Versatile board.
304 bool "ARM Ltd. Versatile Express family"
305 select ARCH_WANT_OPTIONAL_GPIOLIB
307 select ARM_TIMER_SP804
309 select HAVE_MACH_CLKDEV
310 select GENERIC_CLOCKEVENTS
312 select HAVE_PATA_PLATFORM
315 select PLAT_VERSATILE
316 select PLAT_VERSATILE_CLCD
318 This enables support for the ARM Ltd Versatile Express boards.
322 select ARCH_REQUIRE_GPIOLIB
326 select NEED_MACH_IO_H if PCCARD
328 This enables support for systems based on Atmel
329 AT91RM9200 and AT91SAM9* processors.
332 bool "Broadcom BCMRING"
336 select ARM_TIMER_SP804
338 select GENERIC_CLOCKEVENTS
339 select ARCH_WANT_OPTIONAL_GPIOLIB
341 Support for Broadcom's BCMRing platform.
344 bool "Calxeda Highbank-based"
345 select ARCH_WANT_OPTIONAL_GPIOLIB
348 select ARM_TIMER_SP804
352 select GENERIC_CLOCKEVENTS
358 Support for the Calxeda Highbank SoC based boards.
361 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
363 select ARCH_USES_GETTIMEOFFSET
364 select NEED_MACH_MEMORY_H
366 Support for Cirrus Logic 711x/721x/731x based boards.
369 bool "Cavium Networks CNS3XXX family"
371 select GENERIC_CLOCKEVENTS
373 select MIGHT_HAVE_CACHE_L2X0
374 select MIGHT_HAVE_PCI
375 select PCI_DOMAINS if PCI
377 Support for Cavium Networks CNS3XXX platform.
380 bool "Cortina Systems Gemini"
382 select ARCH_REQUIRE_GPIOLIB
383 select ARCH_USES_GETTIMEOFFSET
385 Support for the Cortina Systems Gemini family SoCs
388 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
391 select GENERIC_CLOCKEVENTS
393 select GENERIC_IRQ_CHIP
394 select MIGHT_HAVE_CACHE_L2X0
400 Support for CSR SiRFSoC ARM Cortex A9 Platform
407 select ARCH_USES_GETTIMEOFFSET
408 select NEED_MACH_IO_H
409 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 select ARCH_REQUIRE_GPIOLIB
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_USES_GETTIMEOFFSET
425 select NEED_MACH_MEMORY_H
427 This enables support for the Cirrus EP93xx series of CPUs.
429 config ARCH_FOOTBRIDGE
433 select GENERIC_CLOCKEVENTS
435 select NEED_MACH_IO_H
436 select NEED_MACH_MEMORY_H
438 Support for systems based on the DC21285 companion chip
439 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
442 bool "Freescale MXC/iMX-based"
443 select GENERIC_CLOCKEVENTS
444 select ARCH_REQUIRE_GPIOLIB
447 select GENERIC_IRQ_CHIP
448 select MULTI_IRQ_HANDLER
450 Support for Freescale MXC/iMX-based family of processors
453 bool "Freescale MXS-based"
454 select GENERIC_CLOCKEVENTS
455 select ARCH_REQUIRE_GPIOLIB
459 select HAVE_CLK_PREPARE
463 Support for Freescale MXS-based family of processors
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
475 bool "Hynix HMS720x-based"
478 select ARCH_USES_GETTIMEOFFSET
480 This enables support for systems based on the Hynix HMS720x
488 select ARCH_SUPPORTS_MSI
490 select NEED_MACH_IO_H
491 select NEED_MACH_MEMORY_H
492 select NEED_RET_TO_USER
494 Support for Intel's IOP13XX (XScale) family of processors.
500 select NEED_MACH_IO_H
501 select NEED_RET_TO_USER
504 select ARCH_REQUIRE_GPIOLIB
506 Support for Intel's 80219 and IOP32X (XScale) family of
513 select NEED_MACH_IO_H
514 select NEED_RET_TO_USER
517 select ARCH_REQUIRE_GPIOLIB
519 Support for Intel's IOP33X (XScale) family of processors.
524 select ARCH_HAS_DMA_SET_COHERENT_MASK
527 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select MIGHT_HAVE_PCI
530 select NEED_MACH_IO_H
531 select DMABOUNCE if PCI
533 Support for Intel's IXP4XX (XScale) family of processors.
539 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
541 select NEED_MACH_IO_H
544 Support for the Marvell Dove SoC 88AP510
547 bool "Marvell Kirkwood"
550 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
552 select NEED_MACH_IO_H
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
562 select ARCH_REQUIRE_GPIOLIB
565 select USB_ARCH_HAS_OHCI
567 select GENERIC_CLOCKEVENTS
570 Support for the NXP LPC32XX family of processors
573 bool "Marvell MV78xx0"
576 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
578 select NEED_MACH_IO_H
581 Support for the following Marvell MV78xx0 series SoCs:
589 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
593 Support for the following Marvell Orion 5x series SoCs:
594 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
595 Orion-2 (5281), Orion-1-90 (6183).
598 bool "Marvell PXA168/910/MMP2"
600 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
607 select GENERIC_ALLOCATOR
609 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
612 bool "Micrel/Kendin KS8695"
614 select ARCH_REQUIRE_GPIOLIB
615 select ARCH_USES_GETTIMEOFFSET
616 select NEED_MACH_MEMORY_H
618 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
619 System-on-Chip devices.
622 bool "Nuvoton W90X900 CPU"
624 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
629 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
630 At present, the w90x900 has been renamed nuc900, regarding
631 the ARM series product line, you can login the following
632 link address to know more.
634 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
635 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
641 select GENERIC_CLOCKEVENTS
645 select MIGHT_HAVE_CACHE_L2X0
646 select NEED_MACH_IO_H if PCI
647 select ARCH_HAS_CPUFREQ
649 This enables support for NVIDIA Tegra based systems (Tegra APX,
650 Tegra 6xx and Tegra 2 series).
652 config ARCH_PICOXCELL
653 bool "Picochip picoXcell"
654 select ARCH_REQUIRE_GPIOLIB
655 select ARM_PATCH_PHYS_VIRT
659 select GENERIC_CLOCKEVENTS
666 This enables support for systems based on the Picochip picoXcell
667 family of Femtocell devices. The picoxcell support requires device tree
671 bool "Philips Nexperia PNX4008 Mobile"
674 select ARCH_USES_GETTIMEOFFSET
676 This enables support for Philips PNX4008 mobile platform.
679 bool "PXA2xx/PXA3xx-based"
682 select ARCH_HAS_CPUFREQ
685 select ARCH_REQUIRE_GPIOLIB
686 select GENERIC_CLOCKEVENTS
691 select MULTI_IRQ_HANDLER
692 select ARM_CPU_SUSPEND if PM
695 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
700 select GENERIC_CLOCKEVENTS
701 select ARCH_REQUIRE_GPIOLIB
704 Support for Qualcomm MSM/QSD based systems. This runs on the
705 apps processor of the MSM/QSD and depends on a shared memory
706 interface to the modem processor which runs the baseband
707 stack and controls some vital subsystems
708 (clock and power control, etc).
711 bool "Renesas SH-Mobile / R-Mobile"
714 select HAVE_MACH_CLKDEV
716 select GENERIC_CLOCKEVENTS
717 select MIGHT_HAVE_CACHE_L2X0
720 select MULTI_IRQ_HANDLER
721 select PM_GENERIC_DOMAINS if PM
722 select NEED_MACH_MEMORY_H
724 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
730 select ARCH_MAY_HAVE_PC_FDC
731 select HAVE_PATA_PLATFORM
734 select ARCH_SPARSEMEM_ENABLE
735 select ARCH_USES_GETTIMEOFFSET
737 select NEED_MACH_IO_H
738 select NEED_MACH_MEMORY_H
740 On the Acorn Risc-PC, Linux can support the internal IDE disk and
741 CD-ROM interface, serial and parallel port, and the floppy drive.
748 select ARCH_SPARSEMEM_ENABLE
750 select ARCH_HAS_CPUFREQ
752 select GENERIC_CLOCKEVENTS
754 select ARCH_REQUIRE_GPIOLIB
756 select NEED_MACH_MEMORY_H
759 Support for StrongARM 11x0 based boards.
762 bool "Samsung S3C24XX SoCs"
764 select ARCH_HAS_CPUFREQ
767 select ARCH_USES_GETTIMEOFFSET
768 select HAVE_S3C2410_I2C if I2C
769 select HAVE_S3C_RTC if RTC_CLASS
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select NEED_MACH_IO_H
773 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
774 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
775 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
776 Samsung SMDK2410 development board (and derivatives).
779 bool "Samsung S3C64XX"
787 select ARCH_USES_GETTIMEOFFSET
788 select ARCH_HAS_CPUFREQ
789 select ARCH_REQUIRE_GPIOLIB
790 select SAMSUNG_CLKSRC
791 select SAMSUNG_IRQ_VIC_TIMER
792 select S3C_GPIO_TRACK
794 select USB_ARCH_HAS_OHCI
795 select SAMSUNG_GPIOLIB_4BIT
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 Samsung S3C64XX series based systems
802 bool "Samsung S5P6440 S5P6450"
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select GENERIC_CLOCKEVENTS
810 select HAVE_S3C2410_I2C if I2C
811 select HAVE_S3C_RTC if RTC_CLASS
813 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
817 bool "Samsung S5PC100"
822 select ARCH_USES_GETTIMEOFFSET
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C_RTC if RTC_CLASS
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 Samsung S5PC100 series based systems
830 bool "Samsung S5PV210/S5PC110"
832 select ARCH_SPARSEMEM_ENABLE
833 select ARCH_HAS_HOLES_MEMORYMODEL
838 select ARCH_HAS_CPUFREQ
839 select GENERIC_CLOCKEVENTS
840 select HAVE_S3C2410_I2C if I2C
841 select HAVE_S3C_RTC if RTC_CLASS
842 select HAVE_S3C2410_WATCHDOG if WATCHDOG
843 select NEED_MACH_MEMORY_H
845 Samsung S5PV210/S5PC110 series based systems
848 bool "SAMSUNG EXYNOS"
850 select ARCH_SPARSEMEM_ENABLE
851 select ARCH_HAS_HOLES_MEMORYMODEL
855 select ARCH_HAS_CPUFREQ
856 select GENERIC_CLOCKEVENTS
857 select HAVE_S3C_RTC if RTC_CLASS
858 select HAVE_S3C2410_I2C if I2C
859 select HAVE_S3C2410_WATCHDOG if WATCHDOG
860 select NEED_MACH_MEMORY_H
862 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
871 select ARCH_USES_GETTIMEOFFSET
872 select NEED_MACH_MEMORY_H
873 select NEED_MACH_IO_H
875 Support for the StrongARM based Digital DNARD machine, also known
876 as "Shark" (<http://www.shark-linux.de/shark.html>).
879 bool "ST-Ericsson U300 Series"
885 select ARM_PATCH_PHYS_VIRT
887 select GENERIC_CLOCKEVENTS
889 select HAVE_MACH_CLKDEV
891 select ARCH_REQUIRE_GPIOLIB
893 Support for ST-Ericsson U300 series mobile platforms.
896 bool "ST-Ericsson U8500 Series"
900 select GENERIC_CLOCKEVENTS
902 select ARCH_REQUIRE_GPIOLIB
903 select ARCH_HAS_CPUFREQ
905 select MIGHT_HAVE_CACHE_L2X0
907 Support for ST-Ericsson's Ux500 architecture
910 bool "STMicroelectronics Nomadik"
915 select GENERIC_CLOCKEVENTS
917 select MIGHT_HAVE_CACHE_L2X0
918 select ARCH_REQUIRE_GPIOLIB
920 Support for the Nomadik platform by ST-Ericsson
924 select GENERIC_CLOCKEVENTS
925 select ARCH_REQUIRE_GPIOLIB
929 select GENERIC_ALLOCATOR
930 select GENERIC_IRQ_CHIP
931 select ARCH_HAS_HOLES_MEMORYMODEL
933 Support for TI's DaVinci platform.
938 select ARCH_REQUIRE_GPIOLIB
939 select ARCH_HAS_CPUFREQ
941 select GENERIC_CLOCKEVENTS
942 select ARCH_HAS_HOLES_MEMORYMODEL
944 Support for TI's OMAP platform (OMAP1/2/3/4).
949 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_CLOCKEVENTS
956 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
959 bool "VIA/WonderMedia 85xx"
962 select ARCH_HAS_CPUFREQ
963 select GENERIC_CLOCKEVENTS
964 select ARCH_REQUIRE_GPIOLIB
967 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
970 bool "Xilinx Zynq ARM Cortex A9 Platform"
972 select GENERIC_CLOCKEVENTS
977 select MIGHT_HAVE_CACHE_L2X0
980 Support for Xilinx Zynq ARM Cortex A9 Platform
984 # This is sorted alphabetically by mach-* pathname. However, plat-*
985 # Kconfigs may be included either alphabetically (according to the
986 # plat- suffix) or along side the corresponding mach-* source.
988 source "arch/arm/mach-at91/Kconfig"
990 source "arch/arm/mach-bcmring/Kconfig"
992 source "arch/arm/mach-clps711x/Kconfig"
994 source "arch/arm/mach-cns3xxx/Kconfig"
996 source "arch/arm/mach-davinci/Kconfig"
998 source "arch/arm/mach-dove/Kconfig"
1000 source "arch/arm/mach-ep93xx/Kconfig"
1002 source "arch/arm/mach-footbridge/Kconfig"
1004 source "arch/arm/mach-gemini/Kconfig"
1006 source "arch/arm/mach-h720x/Kconfig"
1008 source "arch/arm/mach-integrator/Kconfig"
1010 source "arch/arm/mach-iop32x/Kconfig"
1012 source "arch/arm/mach-iop33x/Kconfig"
1014 source "arch/arm/mach-iop13xx/Kconfig"
1016 source "arch/arm/mach-ixp4xx/Kconfig"
1018 source "arch/arm/mach-kirkwood/Kconfig"
1020 source "arch/arm/mach-ks8695/Kconfig"
1022 source "arch/arm/mach-msm/Kconfig"
1024 source "arch/arm/mach-mv78xx0/Kconfig"
1026 source "arch/arm/plat-mxc/Kconfig"
1028 source "arch/arm/mach-mxs/Kconfig"
1030 source "arch/arm/mach-netx/Kconfig"
1032 source "arch/arm/mach-nomadik/Kconfig"
1033 source "arch/arm/plat-nomadik/Kconfig"
1035 source "arch/arm/plat-omap/Kconfig"
1037 source "arch/arm/mach-omap1/Kconfig"
1039 source "arch/arm/mach-omap2/Kconfig"
1041 source "arch/arm/mach-orion5x/Kconfig"
1043 source "arch/arm/mach-pxa/Kconfig"
1044 source "arch/arm/plat-pxa/Kconfig"
1046 source "arch/arm/mach-mmp/Kconfig"
1048 source "arch/arm/mach-realview/Kconfig"
1050 source "arch/arm/mach-sa1100/Kconfig"
1052 source "arch/arm/plat-samsung/Kconfig"
1053 source "arch/arm/plat-s3c24xx/Kconfig"
1055 source "arch/arm/plat-spear/Kconfig"
1057 source "arch/arm/mach-s3c24xx/Kconfig"
1059 source "arch/arm/mach-s3c2412/Kconfig"
1060 source "arch/arm/mach-s3c2440/Kconfig"
1064 source "arch/arm/mach-s3c64xx/Kconfig"
1067 source "arch/arm/mach-s5p64x0/Kconfig"
1069 source "arch/arm/mach-s5pc100/Kconfig"
1071 source "arch/arm/mach-s5pv210/Kconfig"
1073 source "arch/arm/mach-exynos/Kconfig"
1075 source "arch/arm/mach-shmobile/Kconfig"
1077 source "arch/arm/mach-tegra/Kconfig"
1079 source "arch/arm/mach-u300/Kconfig"
1081 source "arch/arm/mach-ux500/Kconfig"
1083 source "arch/arm/mach-versatile/Kconfig"
1085 source "arch/arm/mach-vexpress/Kconfig"
1086 source "arch/arm/plat-versatile/Kconfig"
1088 source "arch/arm/mach-vt8500/Kconfig"
1090 source "arch/arm/mach-w90x900/Kconfig"
1092 # Definitions to make life easier
1098 select GENERIC_CLOCKEVENTS
1103 select GENERIC_IRQ_CHIP
1109 config PLAT_VERSATILE
1112 config ARM_TIMER_SP804
1115 select HAVE_SCHED_CLOCK
1117 source arch/arm/mm/Kconfig
1121 default 16 if ARCH_EP93XX
1125 bool "Enable iWMMXt support"
1126 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1127 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1129 Enable support for iWMMXt context switching at run time if
1130 running on a CPU that supports it.
1134 depends on CPU_XSCALE
1138 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1139 (!ARCH_OMAP3 || OMAP3_EMU)
1143 config MULTI_IRQ_HANDLER
1146 Allow each machine to specify it's own IRQ handler at run time.
1149 source "arch/arm/Kconfig-nommu"
1152 config ARM_ERRATA_326103
1153 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1156 Executing a SWP instruction to read-only memory does not set bit 11
1157 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1158 treat the access as a read, preventing a COW from occurring and
1159 causing the faulting task to livelock.
1161 config ARM_ERRATA_411920
1162 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1163 depends on CPU_V6 || CPU_V6K
1165 Invalidation of the Instruction Cache operation can
1166 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1167 It does not affect the MPCore. This option enables the ARM Ltd.
1168 recommended workaround.
1170 config ARM_ERRATA_430973
1171 bool "ARM errata: Stale prediction on replaced interworking branch"
1174 This option enables the workaround for the 430973 Cortex-A8
1175 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1176 interworking branch is replaced with another code sequence at the
1177 same virtual address, whether due to self-modifying code or virtual
1178 to physical address re-mapping, Cortex-A8 does not recover from the
1179 stale interworking branch prediction. This results in Cortex-A8
1180 executing the new code sequence in the incorrect ARM or Thumb state.
1181 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1182 and also flushes the branch target cache at every context switch.
1183 Note that setting specific bits in the ACTLR register may not be
1184 available in non-secure mode.
1186 config ARM_ERRATA_458693
1187 bool "ARM errata: Processor deadlock when a false hazard is created"
1190 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1191 erratum. For very specific sequences of memory operations, it is
1192 possible for a hazard condition intended for a cache line to instead
1193 be incorrectly associated with a different cache line. This false
1194 hazard might then cause a processor deadlock. The workaround enables
1195 the L1 caching of the NEON accesses and disables the PLD instruction
1196 in the ACTLR register. Note that setting specific bits in the ACTLR
1197 register may not be available in non-secure mode.
1199 config ARM_ERRATA_460075
1200 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1203 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1204 erratum. Any asynchronous access to the L2 cache may encounter a
1205 situation in which recent store transactions to the L2 cache are lost
1206 and overwritten with stale memory contents from external memory. The
1207 workaround disables the write-allocate mode for the L2 cache via the
1208 ACTLR register. Note that setting specific bits in the ACTLR register
1209 may not be available in non-secure mode.
1211 config ARM_ERRATA_742230
1212 bool "ARM errata: DMB operation may be faulty"
1213 depends on CPU_V7 && SMP
1215 This option enables the workaround for the 742230 Cortex-A9
1216 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1217 between two write operations may not ensure the correct visibility
1218 ordering of the two writes. This workaround sets a specific bit in
1219 the diagnostic register of the Cortex-A9 which causes the DMB
1220 instruction to behave as a DSB, ensuring the correct behaviour of
1223 config ARM_ERRATA_742231
1224 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1225 depends on CPU_V7 && SMP
1227 This option enables the workaround for the 742231 Cortex-A9
1228 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1229 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1230 accessing some data located in the same cache line, may get corrupted
1231 data due to bad handling of the address hazard when the line gets
1232 replaced from one of the CPUs at the same time as another CPU is
1233 accessing it. This workaround sets specific bits in the diagnostic
1234 register of the Cortex-A9 which reduces the linefill issuing
1235 capabilities of the processor.
1237 config PL310_ERRATA_588369
1238 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1239 depends on CACHE_L2X0
1241 The PL310 L2 cache controller implements three types of Clean &
1242 Invalidate maintenance operations: by Physical Address
1243 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1244 They are architecturally defined to behave as the execution of a
1245 clean operation followed immediately by an invalidate operation,
1246 both performing to the same memory location. This functionality
1247 is not correctly implemented in PL310 as clean lines are not
1248 invalidated as a result of these operations.
1250 config ARM_ERRATA_720789
1251 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1254 This option enables the workaround for the 720789 Cortex-A9 (prior to
1255 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1256 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1257 As a consequence of this erratum, some TLB entries which should be
1258 invalidated are not, resulting in an incoherency in the system page
1259 tables. The workaround changes the TLB flushing routines to invalidate
1260 entries regardless of the ASID.
1262 config PL310_ERRATA_727915
1263 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1264 depends on CACHE_L2X0
1266 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1267 operation (offset 0x7FC). This operation runs in background so that
1268 PL310 can handle normal accesses while it is in progress. Under very
1269 rare circumstances, due to this erratum, write data can be lost when
1270 PL310 treats a cacheable write transaction during a Clean &
1271 Invalidate by Way operation.
1273 config ARM_ERRATA_743622
1274 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1277 This option enables the workaround for the 743622 Cortex-A9
1278 (r2p*) erratum. Under very rare conditions, a faulty
1279 optimisation in the Cortex-A9 Store Buffer may lead to data
1280 corruption. This workaround sets a specific bit in the diagnostic
1281 register of the Cortex-A9 which disables the Store Buffer
1282 optimisation, preventing the defect from occurring. This has no
1283 visible impact on the overall performance or power consumption of the
1286 config ARM_ERRATA_751472
1287 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1290 This option enables the workaround for the 751472 Cortex-A9 (prior
1291 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1292 completion of a following broadcasted operation if the second
1293 operation is received by a CPU before the ICIALLUIS has completed,
1294 potentially leading to corrupted entries in the cache or TLB.
1296 config PL310_ERRATA_753970
1297 bool "PL310 errata: cache sync operation may be faulty"
1298 depends on CACHE_PL310
1300 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1302 Under some condition the effect of cache sync operation on
1303 the store buffer still remains when the operation completes.
1304 This means that the store buffer is always asked to drain and
1305 this prevents it from merging any further writes. The workaround
1306 is to replace the normal offset of cache sync operation (0x730)
1307 by another offset targeting an unmapped PL310 register 0x740.
1308 This has the same effect as the cache sync operation: store buffer
1309 drain and waiting for all buffers empty.
1311 config ARM_ERRATA_754322
1312 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1315 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1316 r3p*) erratum. A speculative memory access may cause a page table walk
1317 which starts prior to an ASID switch but completes afterwards. This
1318 can populate the micro-TLB with a stale entry which may be hit with
1319 the new ASID. This workaround places two dsb instructions in the mm
1320 switching code so that no page table walks can cross the ASID switch.
1322 config ARM_ERRATA_754327
1323 bool "ARM errata: no automatic Store Buffer drain"
1324 depends on CPU_V7 && SMP
1326 This option enables the workaround for the 754327 Cortex-A9 (prior to
1327 r2p0) erratum. The Store Buffer does not have any automatic draining
1328 mechanism and therefore a livelock may occur if an external agent
1329 continuously polls a memory location waiting to observe an update.
1330 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1331 written polling loops from denying visibility of updates to memory.
1333 config ARM_ERRATA_364296
1334 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1335 depends on CPU_V6 && !SMP
1337 This options enables the workaround for the 364296 ARM1136
1338 r0p2 erratum (possible cache data corruption with
1339 hit-under-miss enabled). It sets the undocumented bit 31 in
1340 the auxiliary control register and the FI bit in the control
1341 register, thus disabling hit-under-miss without putting the
1342 processor into full low interrupt latency mode. ARM11MPCore
1345 config ARM_ERRATA_764369
1346 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1347 depends on CPU_V7 && SMP
1349 This option enables the workaround for erratum 764369
1350 affecting Cortex-A9 MPCore with two or more processors (all
1351 current revisions). Under certain timing circumstances, a data
1352 cache line maintenance operation by MVA targeting an Inner
1353 Shareable memory region may fail to proceed up to either the
1354 Point of Coherency or to the Point of Unification of the
1355 system. This workaround adds a DSB instruction before the
1356 relevant cache maintenance functions and sets a specific bit
1357 in the diagnostic control register of the SCU.
1359 config PL310_ERRATA_769419
1360 bool "PL310 errata: no automatic Store Buffer drain"
1361 depends on CACHE_L2X0
1363 On revisions of the PL310 prior to r3p2, the Store Buffer does
1364 not automatically drain. This can cause normal, non-cacheable
1365 writes to be retained when the memory system is idle, leading
1366 to suboptimal I/O performance for drivers using coherent DMA.
1367 This option adds a write barrier to the cpu_idle loop so that,
1368 on systems with an outer cache, the store buffer is drained
1373 source "arch/arm/common/Kconfig"
1383 Find out whether you have ISA slots on your motherboard. ISA is the
1384 name of a bus system, i.e. the way the CPU talks to the other stuff
1385 inside your box. Other bus systems are PCI, EISA, MicroChannel
1386 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1387 newer boards don't support it. If you have ISA, say Y, otherwise N.
1389 # Select ISA DMA controller support
1394 # Select ISA DMA interface
1399 bool "PCI support" if MIGHT_HAVE_PCI
1401 Find out whether you have a PCI motherboard. PCI is the name of a
1402 bus system, i.e. the way the CPU talks to the other stuff inside
1403 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1404 VESA. If you have PCI, say Y, otherwise N.
1410 config PCI_NANOENGINE
1411 bool "BSE nanoEngine PCI support"
1412 depends on SA1100_NANOENGINE
1414 Enable PCI on the BSE nanoEngine board.
1419 # Select the host bridge type
1420 config PCI_HOST_VIA82C505
1422 depends on PCI && ARCH_SHARK
1425 config PCI_HOST_ITE8152
1427 depends on PCI && MACH_ARMCORE
1431 source "drivers/pci/Kconfig"
1433 source "drivers/pcmcia/Kconfig"
1437 menu "Kernel Features"
1442 This option should be selected by machines which have an SMP-
1445 The only effect of this option is to make the SMP-related
1446 options available to the user for configuration.
1449 bool "Symmetric Multi-Processing"
1450 depends on CPU_V6K || CPU_V7
1451 depends on GENERIC_CLOCKEVENTS
1454 select USE_GENERIC_SMP_HELPERS
1455 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1457 This enables support for systems with more than one CPU. If you have
1458 a system with only one CPU, like most personal computers, say N. If
1459 you have a system with more than one CPU, say Y.
1461 If you say N here, the kernel will run on single and multiprocessor
1462 machines, but will use only one CPU of a multiprocessor machine. If
1463 you say Y here, the kernel will run on many, but not all, single
1464 processor machines. On a single processor machine, the kernel will
1465 run faster if you say N here.
1467 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1468 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1469 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1471 If you don't know what to do here, say N.
1474 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1475 depends on EXPERIMENTAL
1476 depends on SMP && !XIP_KERNEL
1479 SMP kernels contain instructions which fail on non-SMP processors.
1480 Enabling this option allows the kernel to modify itself to make
1481 these instructions safe. Disabling it allows about 1K of space
1484 If you don't know what to do here, say Y.
1486 config ARM_CPU_TOPOLOGY
1487 bool "Support cpu topology definition"
1488 depends on SMP && CPU_V7
1491 Support ARM cpu topology definition. The MPIDR register defines
1492 affinity between processors which is then used to describe the cpu
1493 topology of an ARM System.
1496 bool "Multi-core scheduler support"
1497 depends on ARM_CPU_TOPOLOGY
1499 Multi-core scheduler support improves the CPU scheduler's decision
1500 making when dealing with multi-core CPU chips at a cost of slightly
1501 increased overhead in some places. If unsure say N here.
1504 bool "SMT scheduler support"
1505 depends on ARM_CPU_TOPOLOGY
1507 Improves the CPU scheduler's decision making when dealing with
1508 MultiThreading at a cost of slightly increased overhead in some
1509 places. If unsure say N here.
1514 This option enables support for the ARM system coherency unit
1516 config ARM_ARCH_TIMER
1517 bool "Architected timer support"
1520 This option enables support for the ARM architected timer
1526 This options enables support for the ARM timer and watchdog unit
1529 prompt "Memory split"
1532 Select the desired split between kernel and user memory.
1534 If you are not absolutely sure what you are doing, leave this
1538 bool "3G/1G user/kernel split"
1540 bool "2G/2G user/kernel split"
1542 bool "1G/3G user/kernel split"
1547 default 0x40000000 if VMSPLIT_1G
1548 default 0x80000000 if VMSPLIT_2G
1552 int "Maximum number of CPUs (2-32)"
1558 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1559 depends on SMP && HOTPLUG && EXPERIMENTAL
1561 Say Y here to experiment with turning CPUs off and on. CPUs
1562 can be controlled through /sys/devices/system/cpu.
1565 bool "Use local timer interrupts"
1568 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1570 Enable support for local timers on SMP platforms, rather then the
1571 legacy IPI broadcast method. Local timers allows the system
1572 accounting to be spread across the timer interval, preventing a
1573 "thundering herd" at every timer tick.
1577 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1578 default 355 if ARCH_U8500
1579 default 264 if MACH_H4700
1582 Maximum number of GPIOs in the system.
1584 If unsure, leave the default value.
1586 source kernel/Kconfig.preempt
1590 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1591 ARCH_S5PV210 || ARCH_EXYNOS4
1592 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1593 default AT91_TIMER_HZ if ARCH_AT91
1594 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1597 config THUMB2_KERNEL
1598 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1599 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1601 select ARM_ASM_UNIFIED
1604 By enabling this option, the kernel will be compiled in
1605 Thumb-2 mode. A compiler/assembler that understand the unified
1606 ARM-Thumb syntax is needed.
1610 config THUMB2_AVOID_R_ARM_THM_JUMP11
1611 bool "Work around buggy Thumb-2 short branch relocations in gas"
1612 depends on THUMB2_KERNEL && MODULES
1615 Various binutils versions can resolve Thumb-2 branches to
1616 locally-defined, preemptible global symbols as short-range "b.n"
1617 branch instructions.
1619 This is a problem, because there's no guarantee the final
1620 destination of the symbol, or any candidate locations for a
1621 trampoline, are within range of the branch. For this reason, the
1622 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1623 relocation in modules at all, and it makes little sense to add
1626 The symptom is that the kernel fails with an "unsupported
1627 relocation" error when loading some modules.
1629 Until fixed tools are available, passing
1630 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1631 code which hits this problem, at the cost of a bit of extra runtime
1632 stack usage in some cases.
1634 The problem is described in more detail at:
1635 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1637 Only Thumb-2 kernels are affected.
1639 Unless you are sure your tools don't have this problem, say Y.
1641 config ARM_ASM_UNIFIED
1645 bool "Use the ARM EABI to compile the kernel"
1647 This option allows for the kernel to be compiled using the latest
1648 ARM ABI (aka EABI). This is only useful if you are using a user
1649 space environment that is also compiled with EABI.
1651 Since there are major incompatibilities between the legacy ABI and
1652 EABI, especially with regard to structure member alignment, this
1653 option also changes the kernel syscall calling convention to
1654 disambiguate both ABIs and allow for backward compatibility support
1655 (selected with CONFIG_OABI_COMPAT).
1657 To use this you need GCC version 4.0.0 or later.
1660 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1661 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1664 This option preserves the old syscall interface along with the
1665 new (ARM EABI) one. It also provides a compatibility layer to
1666 intercept syscalls that have structure arguments which layout
1667 in memory differs between the legacy ABI and the new ARM EABI
1668 (only for non "thumb" binaries). This option adds a tiny
1669 overhead to all syscalls and produces a slightly larger kernel.
1670 If you know you'll be using only pure EABI user space then you
1671 can say N here. If this option is not selected and you attempt
1672 to execute a legacy ABI binary then the result will be
1673 UNPREDICTABLE (in fact it can be predicted that it won't work
1674 at all). If in doubt say Y.
1676 config ARCH_HAS_HOLES_MEMORYMODEL
1679 config ARCH_SPARSEMEM_ENABLE
1682 config ARCH_SPARSEMEM_DEFAULT
1683 def_bool ARCH_SPARSEMEM_ENABLE
1685 config ARCH_SELECT_MEMORY_MODEL
1686 def_bool ARCH_SPARSEMEM_ENABLE
1688 config HAVE_ARCH_PFN_VALID
1689 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1692 bool "High Memory Support"
1695 The address space of ARM processors is only 4 Gigabytes large
1696 and it has to accommodate user address space, kernel address
1697 space as well as some memory mapped IO. That means that, if you
1698 have a large amount of physical memory and/or IO, not all of the
1699 memory can be "permanently mapped" by the kernel. The physical
1700 memory that is not permanently mapped is called "high memory".
1702 Depending on the selected kernel/user memory split, minimum
1703 vmalloc space and actual amount of RAM, you may not need this
1704 option which should result in a slightly faster kernel.
1709 bool "Allocate 2nd-level pagetables from highmem"
1712 config HW_PERF_EVENTS
1713 bool "Enable hardware performance counter support for perf events"
1714 depends on PERF_EVENTS && CPU_HAS_PMU
1717 Enable hardware performance counter support for perf events. If
1718 disabled, perf events will use software events only.
1722 config FORCE_MAX_ZONEORDER
1723 int "Maximum zone order" if ARCH_SHMOBILE
1724 range 11 64 if ARCH_SHMOBILE
1725 default "9" if SA1111
1728 The kernel memory allocator divides physically contiguous memory
1729 blocks into "zones", where each zone is a power of two number of
1730 pages. This option selects the largest power of two that the kernel
1731 keeps in the memory allocator. If you need to allocate very large
1732 blocks of physically contiguous memory, then you may need to
1733 increase this value.
1735 This config option is actually maximum order plus one. For example,
1736 a value of 11 means that the largest free memory block is 2^10 pages.
1739 bool "Timer and CPU usage LEDs"
1740 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1741 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1742 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1743 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1744 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1745 ARCH_AT91 || ARCH_DAVINCI || \
1746 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1748 If you say Y here, the LEDs on your machine will be used
1749 to provide useful information about your current system status.
1751 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1752 be able to select which LEDs are active using the options below. If
1753 you are compiling a kernel for the EBSA-110 or the LART however, the
1754 red LED will simply flash regularly to indicate that the system is
1755 still functional. It is safe to say Y here if you have a CATS
1756 system, but the driver will do nothing.
1759 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1760 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1761 || MACH_OMAP_PERSEUS2
1763 depends on !GENERIC_CLOCKEVENTS
1764 default y if ARCH_EBSA110
1766 If you say Y here, one of the system LEDs (the green one on the
1767 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1768 will flash regularly to indicate that the system is still
1769 operational. This is mainly useful to kernel hackers who are
1770 debugging unstable kernels.
1772 The LART uses the same LED for both Timer LED and CPU usage LED
1773 functions. You may choose to use both, but the Timer LED function
1774 will overrule the CPU usage LED.
1777 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1779 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1780 || MACH_OMAP_PERSEUS2
1783 If you say Y here, the red LED will be used to give a good real
1784 time indication of CPU usage, by lighting whenever the idle task
1785 is not currently executing.
1787 The LART uses the same LED for both Timer LED and CPU usage LED
1788 functions. You may choose to use both, but the Timer LED function
1789 will overrule the CPU usage LED.
1791 config ALIGNMENT_TRAP
1793 depends on CPU_CP15_MMU
1794 default y if !ARCH_EBSA110
1795 select HAVE_PROC_CPU if PROC_FS
1797 ARM processors cannot fetch/store information which is not
1798 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1799 address divisible by 4. On 32-bit ARM processors, these non-aligned
1800 fetch/store instructions will be emulated in software if you say
1801 here, which has a severe performance impact. This is necessary for
1802 correct operation of some network protocols. With an IP-only
1803 configuration it is safe to say N, otherwise say Y.
1805 config UACCESS_WITH_MEMCPY
1806 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1807 depends on MMU && EXPERIMENTAL
1808 default y if CPU_FEROCEON
1810 Implement faster copy_to_user and clear_user methods for CPU
1811 cores where a 8-word STM instruction give significantly higher
1812 memory write throughput than a sequence of individual 32bit stores.
1814 A possible side effect is a slight increase in scheduling latency
1815 between threads sharing the same address space if they invoke
1816 such copy operations with large buffers.
1818 However, if the CPU data cache is using a write-allocate mode,
1819 this option is unlikely to provide any performance gain.
1823 prompt "Enable seccomp to safely compute untrusted bytecode"
1825 This kernel feature is useful for number crunching applications
1826 that may need to compute untrusted bytecode during their
1827 execution. By using pipes or other transports made available to
1828 the process as file descriptors supporting the read/write
1829 syscalls, it's possible to isolate those applications in
1830 their own address space using seccomp. Once seccomp is
1831 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1832 and the task is only allowed to execute a few safe syscalls
1833 defined by each seccomp mode.
1835 config CC_STACKPROTECTOR
1836 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1837 depends on EXPERIMENTAL
1839 This option turns on the -fstack-protector GCC feature. This
1840 feature puts, at the beginning of functions, a canary value on
1841 the stack just before the return address, and validates
1842 the value just before actually returning. Stack based buffer
1843 overflows (that need to overwrite this return address) now also
1844 overwrite the canary, which gets detected and the attack is then
1845 neutralized via a kernel panic.
1846 This feature requires gcc version 4.2 or above.
1848 config DEPRECATED_PARAM_STRUCT
1849 bool "Provide old way to pass kernel parameters"
1851 This was deprecated in 2001 and announced to live on for 5 years.
1852 Some old boot loaders still use this way.
1859 bool "Flattened Device Tree support"
1861 select OF_EARLY_FLATTREE
1864 Include support for flattened device tree machine descriptions.
1866 # Compressed boot loader in ROM. Yes, we really want to ask about
1867 # TEXT and BSS so we preserve their values in the config files.
1868 config ZBOOT_ROM_TEXT
1869 hex "Compressed ROM boot loader base address"
1872 The physical address at which the ROM-able zImage is to be
1873 placed in the target. Platforms which normally make use of
1874 ROM-able zImage formats normally set this to a suitable
1875 value in their defconfig file.
1877 If ZBOOT_ROM is not enabled, this has no effect.
1879 config ZBOOT_ROM_BSS
1880 hex "Compressed ROM boot loader BSS address"
1883 The base address of an area of read/write memory in the target
1884 for the ROM-able zImage which must be available while the
1885 decompressor is running. It must be large enough to hold the
1886 entire decompressed kernel plus an additional 128 KiB.
1887 Platforms which normally make use of ROM-able zImage formats
1888 normally set this to a suitable value in their defconfig file.
1890 If ZBOOT_ROM is not enabled, this has no effect.
1893 bool "Compressed boot loader in ROM/flash"
1894 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1896 Say Y here if you intend to execute your compressed kernel image
1897 (zImage) directly from ROM or flash. If unsure, say N.
1900 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1901 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1902 default ZBOOT_ROM_NONE
1904 Include experimental SD/MMC loading code in the ROM-able zImage.
1905 With this enabled it is possible to write the ROM-able zImage
1906 kernel image to an MMC or SD card and boot the kernel straight
1907 from the reset vector. At reset the processor Mask ROM will load
1908 the first part of the ROM-able zImage which in turn loads the
1909 rest the kernel image to RAM.
1911 config ZBOOT_ROM_NONE
1912 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1914 Do not load image from SD or MMC
1916 config ZBOOT_ROM_MMCIF
1917 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1919 Load image from MMCIF hardware block.
1921 config ZBOOT_ROM_SH_MOBILE_SDHI
1922 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1924 Load image from SDHI hardware block
1928 config ARM_APPENDED_DTB
1929 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1930 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1932 With this option, the boot code will look for a device tree binary
1933 (DTB) appended to zImage
1934 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1936 This is meant as a backward compatibility convenience for those
1937 systems with a bootloader that can't be upgraded to accommodate
1938 the documented boot protocol using a device tree.
1940 Beware that there is very little in terms of protection against
1941 this option being confused by leftover garbage in memory that might
1942 look like a DTB header after a reboot if no actual DTB is appended
1943 to zImage. Do not leave this option active in a production kernel
1944 if you don't intend to always append a DTB. Proper passing of the
1945 location into r2 of a bootloader provided DTB is always preferable
1948 config ARM_ATAG_DTB_COMPAT
1949 bool "Supplement the appended DTB with traditional ATAG information"
1950 depends on ARM_APPENDED_DTB
1952 Some old bootloaders can't be updated to a DTB capable one, yet
1953 they provide ATAGs with memory configuration, the ramdisk address,
1954 the kernel cmdline string, etc. Such information is dynamically
1955 provided by the bootloader and can't always be stored in a static
1956 DTB. To allow a device tree enabled kernel to be used with such
1957 bootloaders, this option allows zImage to extract the information
1958 from the ATAG list and store it at run time into the appended DTB.
1961 string "Default kernel command string"
1964 On some architectures (EBSA110 and CATS), there is currently no way
1965 for the boot loader to pass arguments to the kernel. For these
1966 architectures, you should supply some command-line options at build
1967 time by entering them here. As a minimum, you should specify the
1968 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1971 prompt "Kernel command line type" if CMDLINE != ""
1972 default CMDLINE_FROM_BOOTLOADER
1974 config CMDLINE_FROM_BOOTLOADER
1975 bool "Use bootloader kernel arguments if available"
1977 Uses the command-line options passed by the boot loader. If
1978 the boot loader doesn't provide any, the default kernel command
1979 string provided in CMDLINE will be used.
1981 config CMDLINE_EXTEND
1982 bool "Extend bootloader kernel arguments"
1984 The command-line arguments provided by the boot loader will be
1985 appended to the default kernel command string.
1987 config CMDLINE_FORCE
1988 bool "Always use the default kernel command string"
1990 Always use the default kernel command string, even if the boot
1991 loader passes other arguments to the kernel.
1992 This is useful if you cannot or don't want to change the
1993 command-line options your boot loader passes to the kernel.
1997 bool "Kernel Execute-In-Place from ROM"
1998 depends on !ZBOOT_ROM && !ARM_LPAE
2000 Execute-In-Place allows the kernel to run from non-volatile storage
2001 directly addressable by the CPU, such as NOR flash. This saves RAM
2002 space since the text section of the kernel is not loaded from flash
2003 to RAM. Read-write sections, such as the data section and stack,
2004 are still copied to RAM. The XIP kernel is not compressed since
2005 it has to run directly from flash, so it will take more space to
2006 store it. The flash address used to link the kernel object files,
2007 and for storing it, is configuration dependent. Therefore, if you
2008 say Y here, you must know the proper physical address where to
2009 store the kernel image depending on your own flash memory usage.
2011 Also note that the make target becomes "make xipImage" rather than
2012 "make zImage" or "make Image". The final kernel binary to put in
2013 ROM memory will be arch/arm/boot/xipImage.
2017 config XIP_PHYS_ADDR
2018 hex "XIP Kernel Physical Location"
2019 depends on XIP_KERNEL
2020 default "0x00080000"
2022 This is the physical address in your flash memory the kernel will
2023 be linked for and stored to. This address is dependent on your
2027 bool "Kexec system call (EXPERIMENTAL)"
2028 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2030 kexec is a system call that implements the ability to shutdown your
2031 current kernel, and to start another kernel. It is like a reboot
2032 but it is independent of the system firmware. And like a reboot
2033 you can start any kernel with it, not just Linux.
2035 It is an ongoing process to be certain the hardware in a machine
2036 is properly shutdown, so do not be surprised if this code does not
2037 initially work for you. It may help to enable device hotplugging
2041 bool "Export atags in procfs"
2045 Should the atags used to boot the kernel be exported in an "atags"
2046 file in procfs. Useful with kexec.
2049 bool "Build kdump crash kernel (EXPERIMENTAL)"
2050 depends on EXPERIMENTAL
2052 Generate crash dump after being started by kexec. This should
2053 be normally only set in special crash dump kernels which are
2054 loaded in the main kernel with kexec-tools into a specially
2055 reserved region and then later executed after a crash by
2056 kdump/kexec. The crash dump kernel must be compiled to a
2057 memory address not used by the main kernel
2059 For more details see Documentation/kdump/kdump.txt
2061 config AUTO_ZRELADDR
2062 bool "Auto calculation of the decompressed kernel image address"
2063 depends on !ZBOOT_ROM && !ARCH_U300
2065 ZRELADDR is the physical address where the decompressed kernel
2066 image will be placed. If AUTO_ZRELADDR is selected, the address
2067 will be determined at run-time by masking the current IP with
2068 0xf8000000. This assumes the zImage being placed in the first 128MB
2069 from start of memory.
2073 menu "CPU Power Management"
2077 source "drivers/cpufreq/Kconfig"
2080 tristate "CPUfreq driver for i.MX CPUs"
2081 depends on ARCH_MXC && CPU_FREQ
2083 This enables the CPUfreq driver for i.MX CPUs.
2085 config CPU_FREQ_SA1100
2088 config CPU_FREQ_SA1110
2091 config CPU_FREQ_INTEGRATOR
2092 tristate "CPUfreq driver for ARM Integrator CPUs"
2093 depends on ARCH_INTEGRATOR && CPU_FREQ
2096 This enables the CPUfreq driver for ARM Integrator CPUs.
2098 For details, take a look at <file:Documentation/cpu-freq>.
2104 depends on CPU_FREQ && ARCH_PXA && PXA25x
2106 select CPU_FREQ_TABLE
2107 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2112 Internal configuration node for common cpufreq on Samsung SoC
2114 config CPU_FREQ_S3C24XX
2115 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2116 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2119 This enables the CPUfreq driver for the Samsung S3C24XX family
2122 For details, take a look at <file:Documentation/cpu-freq>.
2126 config CPU_FREQ_S3C24XX_PLL
2127 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2128 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2130 Compile in support for changing the PLL frequency from the
2131 S3C24XX series CPUfreq driver. The PLL takes time to settle
2132 after a frequency change, so by default it is not enabled.
2134 This also means that the PLL tables for the selected CPU(s) will
2135 be built which may increase the size of the kernel image.
2137 config CPU_FREQ_S3C24XX_DEBUG
2138 bool "Debug CPUfreq Samsung driver core"
2139 depends on CPU_FREQ_S3C24XX
2141 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2143 config CPU_FREQ_S3C24XX_IODEBUG
2144 bool "Debug CPUfreq Samsung driver IO timing"
2145 depends on CPU_FREQ_S3C24XX
2147 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2149 config CPU_FREQ_S3C24XX_DEBUGFS
2150 bool "Export debugfs for CPUFreq"
2151 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2153 Export status information via debugfs.
2157 source "drivers/cpuidle/Kconfig"
2161 menu "Floating point emulation"
2163 comment "At least one emulation must be selected"
2166 bool "NWFPE math emulation"
2167 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2169 Say Y to include the NWFPE floating point emulator in the kernel.
2170 This is necessary to run most binaries. Linux does not currently
2171 support floating point hardware so you need to say Y here even if
2172 your machine has an FPA or floating point co-processor podule.
2174 You may say N here if you are going to load the Acorn FPEmulator
2175 early in the bootup.
2178 bool "Support extended precision"
2179 depends on FPE_NWFPE
2181 Say Y to include 80-bit support in the kernel floating-point
2182 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2183 Note that gcc does not generate 80-bit operations by default,
2184 so in most cases this option only enlarges the size of the
2185 floating point emulator without any good reason.
2187 You almost surely want to say N here.
2190 bool "FastFPE math emulation (EXPERIMENTAL)"
2191 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2193 Say Y here to include the FAST floating point emulator in the kernel.
2194 This is an experimental much faster emulator which now also has full
2195 precision for the mantissa. It does not support any exceptions.
2196 It is very simple, and approximately 3-6 times faster than NWFPE.
2198 It should be sufficient for most programs. It may be not suitable
2199 for scientific calculations, but you have to check this for yourself.
2200 If you do not feel you need a faster FP emulation you should better
2204 bool "VFP-format floating point maths"
2205 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2207 Say Y to include VFP support code in the kernel. This is needed
2208 if your hardware includes a VFP unit.
2210 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2211 release notes and additional status information.
2213 Say N if your target does not have VFP hardware.
2221 bool "Advanced SIMD (NEON) Extension support"
2222 depends on VFPv3 && CPU_V7
2224 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2229 menu "Userspace binary formats"
2231 source "fs/Kconfig.binfmt"
2234 tristate "RISC OS personality"
2237 Say Y here to include the kernel code necessary if you want to run
2238 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2239 experimental; if this sounds frightening, say N and sleep in peace.
2240 You can also say M here to compile this support as a module (which
2241 will be called arthur).
2245 menu "Power management options"
2247 source "kernel/power/Kconfig"
2249 config ARCH_SUSPEND_POSSIBLE
2250 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2251 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2252 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2255 config ARM_CPU_SUSPEND
2260 source "net/Kconfig"
2262 source "drivers/Kconfig"
2266 source "arch/arm/Kconfig.debug"
2268 source "security/Kconfig"
2270 source "crypto/Kconfig"
2272 source "lib/Kconfig"