4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
316 select ARM_PATCH_PHYS_VIRT
319 select COMMON_CLK_VERSATILE
320 select GENERIC_CLOCKEVENTS
323 select MULTI_IRQ_HANDLER
324 select NEED_MACH_MEMORY_H
325 select PLAT_VERSATILE
328 select VERSATILE_FPGA_IRQ
330 Support for ARM's Integrator platform.
333 bool "ARM Ltd. RealView family"
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_TIMER_SP804
338 select COMMON_CLK_VERSATILE
339 select GENERIC_CLOCKEVENTS
340 select GPIO_PL061 if GPIOLIB
342 select NEED_MACH_MEMORY_H
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
346 This enables support for ARM Ltd RealView boards.
348 config ARCH_VERSATILE
349 bool "ARM Ltd. Versatile family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
356 select HAVE_MACH_CLKDEV
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_CLCD
360 select PLAT_VERSATILE_CLOCK
361 select VERSATILE_FPGA_IRQ
363 This enables support for ARM Ltd Versatile board.
367 select ARCH_REQUIRE_GPIOLIB
370 select NEED_MACH_GPIO_H
371 select NEED_MACH_IO_H if PCCARD
373 select PINCTRL_AT91 if USE_OF
375 This enables support for systems based on Atmel
376 AT91RM9200 and AT91SAM9* processors.
379 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
380 select ARCH_REQUIRE_GPIOLIB
385 select GENERIC_CLOCKEVENTS
387 select MULTI_IRQ_HANDLER
390 Support for Cirrus Logic 711x/721x/731x based boards.
393 bool "Cortina Systems Gemini"
394 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
399 Support for the Cortina Systems Gemini family SoCs
403 select ARCH_USES_GETTIMEOFFSET
406 select NEED_MACH_IO_H
407 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
417 select ARCH_HAS_HOLES_MEMORYMODEL
418 select ARCH_REQUIRE_GPIOLIB
419 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Hilscher NetX based"
445 select GENERIC_CLOCKEVENTS
447 This enables support for systems based on the Hilscher NetX Soc
453 select NEED_MACH_MEMORY_H
454 select NEED_RET_TO_USER
459 Support for Intel's IOP13XX (XScale) family of processors.
464 select ARCH_REQUIRE_GPIOLIB
467 select NEED_RET_TO_USER
471 Support for Intel's 80219 and IOP32X (XScale) family of
477 select ARCH_REQUIRE_GPIOLIB
480 select NEED_RET_TO_USER
484 Support for Intel's IOP33X (XScale) family of processors.
489 select ARCH_HAS_DMA_SET_COHERENT_MASK
490 select ARCH_SUPPORTS_BIG_ENDIAN
491 select ARCH_REQUIRE_GPIOLIB
494 select DMABOUNCE if PCI
495 select GENERIC_CLOCKEVENTS
496 select MIGHT_HAVE_PCI
497 select NEED_MACH_IO_H
498 select USB_EHCI_BIG_ENDIAN_DESC
499 select USB_EHCI_BIG_ENDIAN_MMIO
501 Support for Intel's IXP4XX (XScale) family of processors.
505 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
508 select MIGHT_HAVE_PCI
512 select PLAT_ORION_LEGACY
513 select USB_ARCH_HAS_EHCI
515 Support for the Marvell Dove SoC 88AP510
518 bool "Marvell Kirkwood"
519 select ARCH_HAS_CPUFREQ
520 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
527 select PINCTRL_KIRKWOOD
528 select PLAT_ORION_LEGACY
530 Support for the following Marvell Kirkwood series SoCs:
531 88F6180, 88F6192 and 88F6281.
534 bool "Marvell MV78xx0"
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
542 Support for the following Marvell MV78xx0 series SoCs:
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Orion 5x series SoCs:
556 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
557 Orion-2 (5281), Orion-1-90 (6183).
560 bool "Marvell PXA168/910/MMP2"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_ALLOCATOR
565 select GENERIC_CLOCKEVENTS
568 select MULTI_IRQ_HANDLER
573 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
576 bool "Micrel/Kendin KS8695"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
581 select NEED_MACH_MEMORY_H
583 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
584 System-on-Chip devices.
587 bool "Nuvoton W90X900 CPU"
588 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
594 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
595 At present, the w90x900 has been renamed nuc900, regarding
596 the ARM series product line, you can login the following
597 link address to know more.
599 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
600 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
604 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
612 select USB_ARCH_HAS_OHCI
615 Support for the NXP LPC32XX family of processors
618 bool "PXA2xx/PXA3xx-based"
620 select ARCH_HAS_CPUFREQ
622 select ARCH_REQUIRE_GPIOLIB
623 select ARM_CPU_SUSPEND if PM
627 select GENERIC_CLOCKEVENTS
630 select MULTI_IRQ_HANDLER
634 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
638 select ARCH_REQUIRE_GPIOLIB
639 select CLKSRC_OF if OF
641 select GENERIC_CLOCKEVENTS
643 Support for Qualcomm MSM/QSD based systems. This runs on the
644 apps processor of the MSM/QSD and depends on a shared memory
645 interface to the modem processor which runs the baseband
646 stack and controls some vital subsystems
647 (clock and power control, etc).
649 config ARCH_SHMOBILE_LEGACY
650 bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
652 select ARM_PATCH_PHYS_VIRT
654 select GENERIC_CLOCKEVENTS
655 select HAVE_ARM_SCU if SMP
656 select HAVE_ARM_TWD if SMP
657 select HAVE_MACH_CLKDEV
659 select MIGHT_HAVE_CACHE_L2X0
660 select MULTI_IRQ_HANDLER
663 select PM_GENERIC_DOMAINS if PM
666 Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
667 a non-multiplatform kernel.
672 select ARCH_MAY_HAVE_PC_FDC
673 select ARCH_SPARSEMEM_ENABLE
674 select ARCH_USES_GETTIMEOFFSET
677 select HAVE_PATA_PLATFORM
679 select NEED_MACH_IO_H
680 select NEED_MACH_MEMORY_H
684 On the Acorn Risc-PC, Linux can support the internal IDE disk and
685 CD-ROM interface, serial and parallel port, and the floppy drive.
689 select ARCH_HAS_CPUFREQ
691 select ARCH_REQUIRE_GPIOLIB
692 select ARCH_SPARSEMEM_ENABLE
697 select GENERIC_CLOCKEVENTS
700 select NEED_MACH_MEMORY_H
703 Support for StrongARM 11x0 based boards.
706 bool "Samsung S3C24XX SoCs"
707 select ARCH_HAS_CPUFREQ
708 select ARCH_REQUIRE_GPIOLIB
710 select CLKSRC_SAMSUNG_PWM
711 select GENERIC_CLOCKEVENTS
713 select HAVE_S3C2410_I2C if I2C
714 select HAVE_S3C2410_WATCHDOG if WATCHDOG
715 select HAVE_S3C_RTC if RTC_CLASS
716 select MULTI_IRQ_HANDLER
717 select NEED_MACH_GPIO_H
718 select NEED_MACH_IO_H
721 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
722 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
723 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
724 Samsung SMDK2410 development board (and derivatives).
727 bool "Samsung S3C64XX"
728 select ARCH_HAS_CPUFREQ
729 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
736 select GENERIC_CLOCKEVENTS
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
741 select NEED_MACH_GPIO_H
744 select PM_GENERIC_DOMAINS
746 select S3C_GPIO_TRACK
748 select SAMSUNG_GPIOLIB_4BIT
749 select SAMSUNG_WAKEMASK
750 select SAMSUNG_WDT_RESET
751 select USB_ARCH_HAS_OHCI
753 Samsung S3C64XX series based systems
756 bool "Samsung S5P6440 S5P6450"
758 select CLKSRC_SAMSUNG_PWM
760 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 select HAVE_S3C_RTC if RTC_CLASS
765 select NEED_MACH_GPIO_H
767 select SAMSUNG_WDT_RESET
769 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
773 bool "Samsung S5PC100"
774 select ARCH_REQUIRE_GPIOLIB
776 select CLKSRC_SAMSUNG_PWM
778 select GENERIC_CLOCKEVENTS
780 select HAVE_S3C2410_I2C if I2C
781 select HAVE_S3C2410_WATCHDOG if WATCHDOG
782 select HAVE_S3C_RTC if RTC_CLASS
783 select NEED_MACH_GPIO_H
785 select SAMSUNG_WDT_RESET
787 Samsung S5PC100 series based systems
790 bool "Samsung S5PV210/S5PC110"
791 select ARCH_HAS_CPUFREQ
792 select ARCH_HAS_HOLES_MEMORYMODEL
793 select ARCH_SPARSEMEM_ENABLE
795 select CLKSRC_SAMSUNG_PWM
797 select GENERIC_CLOCKEVENTS
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select HAVE_S3C_RTC if RTC_CLASS
802 select NEED_MACH_GPIO_H
803 select NEED_MACH_MEMORY_H
806 Samsung S5PV210/S5PC110 series based systems
809 bool "Samsung EXYNOS"
810 select ARCH_HAS_CPUFREQ
811 select ARCH_HAS_HOLES_MEMORYMODEL
812 select ARCH_REQUIRE_GPIOLIB
813 select ARCH_SPARSEMEM_ENABLE
817 select GENERIC_CLOCKEVENTS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select HAVE_S3C_RTC if RTC_CLASS
821 select NEED_MACH_MEMORY_H
825 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
829 select ARCH_HAS_HOLES_MEMORYMODEL
830 select ARCH_REQUIRE_GPIOLIB
832 select GENERIC_ALLOCATOR
833 select GENERIC_CLOCKEVENTS
834 select GENERIC_IRQ_CHIP
840 Support for TI's DaVinci platform.
845 select ARCH_HAS_CPUFREQ
846 select ARCH_HAS_HOLES_MEMORYMODEL
848 select ARCH_REQUIRE_GPIOLIB
851 select GENERIC_CLOCKEVENTS
852 select GENERIC_IRQ_CHIP
855 select NEED_MACH_IO_H if PCCARD
856 select NEED_MACH_MEMORY_H
858 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
862 menu "Multiple platform selection"
863 depends on ARCH_MULTIPLATFORM
865 comment "CPU Core family selection"
867 config ARCH_MULTI_V4T
868 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
869 depends on !ARCH_MULTI_V6_V7
870 select ARCH_MULTI_V4_V5
871 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
872 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
873 CPU_ARM925T || CPU_ARM940T)
876 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
877 depends on !ARCH_MULTI_V6_V7
878 select ARCH_MULTI_V4_V5
879 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
880 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
881 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
883 config ARCH_MULTI_V4_V5
887 bool "ARMv6 based platforms (ARM11)"
888 select ARCH_MULTI_V6_V7
892 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
894 select ARCH_MULTI_V6_V7
897 config ARCH_MULTI_V6_V7
900 config ARCH_MULTI_CPU_AUTO
901 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
907 # This is sorted alphabetically by mach-* pathname. However, plat-*
908 # Kconfigs may be included either alphabetically (according to the
909 # plat- suffix) or along side the corresponding mach-* source.
911 source "arch/arm/mach-mvebu/Kconfig"
913 source "arch/arm/mach-at91/Kconfig"
915 source "arch/arm/mach-bcm/Kconfig"
917 source "arch/arm/mach-bcm2835/Kconfig"
919 source "arch/arm/mach-clps711x/Kconfig"
921 source "arch/arm/mach-cns3xxx/Kconfig"
923 source "arch/arm/mach-davinci/Kconfig"
925 source "arch/arm/mach-dove/Kconfig"
927 source "arch/arm/mach-ep93xx/Kconfig"
929 source "arch/arm/mach-footbridge/Kconfig"
931 source "arch/arm/mach-gemini/Kconfig"
933 source "arch/arm/mach-highbank/Kconfig"
935 source "arch/arm/mach-integrator/Kconfig"
937 source "arch/arm/mach-iop32x/Kconfig"
939 source "arch/arm/mach-iop33x/Kconfig"
941 source "arch/arm/mach-iop13xx/Kconfig"
943 source "arch/arm/mach-ixp4xx/Kconfig"
945 source "arch/arm/mach-keystone/Kconfig"
947 source "arch/arm/mach-kirkwood/Kconfig"
949 source "arch/arm/mach-ks8695/Kconfig"
951 source "arch/arm/mach-msm/Kconfig"
953 source "arch/arm/mach-mv78xx0/Kconfig"
955 source "arch/arm/mach-imx/Kconfig"
957 source "arch/arm/mach-mxs/Kconfig"
959 source "arch/arm/mach-netx/Kconfig"
961 source "arch/arm/mach-nomadik/Kconfig"
963 source "arch/arm/mach-nspire/Kconfig"
965 source "arch/arm/plat-omap/Kconfig"
967 source "arch/arm/mach-omap1/Kconfig"
969 source "arch/arm/mach-omap2/Kconfig"
971 source "arch/arm/mach-orion5x/Kconfig"
973 source "arch/arm/mach-picoxcell/Kconfig"
975 source "arch/arm/mach-pxa/Kconfig"
976 source "arch/arm/plat-pxa/Kconfig"
978 source "arch/arm/mach-mmp/Kconfig"
980 source "arch/arm/mach-realview/Kconfig"
982 source "arch/arm/mach-rockchip/Kconfig"
984 source "arch/arm/mach-sa1100/Kconfig"
986 source "arch/arm/plat-samsung/Kconfig"
988 source "arch/arm/mach-socfpga/Kconfig"
990 source "arch/arm/mach-spear/Kconfig"
992 source "arch/arm/mach-sti/Kconfig"
994 source "arch/arm/mach-s3c24xx/Kconfig"
996 source "arch/arm/mach-s3c64xx/Kconfig"
998 source "arch/arm/mach-s5p64x0/Kconfig"
1000 source "arch/arm/mach-s5pc100/Kconfig"
1002 source "arch/arm/mach-s5pv210/Kconfig"
1004 source "arch/arm/mach-exynos/Kconfig"
1006 source "arch/arm/mach-shmobile/Kconfig"
1008 source "arch/arm/mach-sunxi/Kconfig"
1010 source "arch/arm/mach-prima2/Kconfig"
1012 source "arch/arm/mach-tegra/Kconfig"
1014 source "arch/arm/mach-u300/Kconfig"
1016 source "arch/arm/mach-ux500/Kconfig"
1018 source "arch/arm/mach-versatile/Kconfig"
1020 source "arch/arm/mach-vexpress/Kconfig"
1021 source "arch/arm/plat-versatile/Kconfig"
1023 source "arch/arm/mach-virt/Kconfig"
1025 source "arch/arm/mach-vt8500/Kconfig"
1027 source "arch/arm/mach-w90x900/Kconfig"
1029 source "arch/arm/mach-zynq/Kconfig"
1031 # Definitions to make life easier
1037 select GENERIC_CLOCKEVENTS
1043 select GENERIC_IRQ_CHIP
1046 config PLAT_ORION_LEGACY
1053 config PLAT_VERSATILE
1056 config ARM_TIMER_SP804
1059 select CLKSRC_OF if OF
1061 source "arch/arm/firmware/Kconfig"
1063 source arch/arm/mm/Kconfig
1067 default 16 if ARCH_EP93XX
1071 bool "Enable iWMMXt support" if !CPU_PJ4
1072 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1073 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1075 Enable support for iWMMXt context switching at run time if
1076 running on a CPU that supports it.
1078 config MULTI_IRQ_HANDLER
1081 Allow each machine to specify it's own IRQ handler at run time.
1084 source "arch/arm/Kconfig-nommu"
1087 config PJ4B_ERRATA_4742
1088 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1089 depends on CPU_PJ4B && MACH_ARMADA_370
1092 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1093 Event (WFE) IDLE states, a specific timing sensitivity exists between
1094 the retiring WFI/WFE instructions and the newly issued subsequent
1095 instructions. This sensitivity can result in a CPU hang scenario.
1097 The software must insert either a Data Synchronization Barrier (DSB)
1098 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1101 config ARM_ERRATA_326103
1102 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1105 Executing a SWP instruction to read-only memory does not set bit 11
1106 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1107 treat the access as a read, preventing a COW from occurring and
1108 causing the faulting task to livelock.
1110 config ARM_ERRATA_411920
1111 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1112 depends on CPU_V6 || CPU_V6K
1114 Invalidation of the Instruction Cache operation can
1115 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1116 It does not affect the MPCore. This option enables the ARM Ltd.
1117 recommended workaround.
1119 config ARM_ERRATA_430973
1120 bool "ARM errata: Stale prediction on replaced interworking branch"
1123 This option enables the workaround for the 430973 Cortex-A8
1124 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1125 interworking branch is replaced with another code sequence at the
1126 same virtual address, whether due to self-modifying code or virtual
1127 to physical address re-mapping, Cortex-A8 does not recover from the
1128 stale interworking branch prediction. This results in Cortex-A8
1129 executing the new code sequence in the incorrect ARM or Thumb state.
1130 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1131 and also flushes the branch target cache at every context switch.
1132 Note that setting specific bits in the ACTLR register may not be
1133 available in non-secure mode.
1135 config ARM_ERRATA_458693
1136 bool "ARM errata: Processor deadlock when a false hazard is created"
1138 depends on !ARCH_MULTIPLATFORM
1140 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1141 erratum. For very specific sequences of memory operations, it is
1142 possible for a hazard condition intended for a cache line to instead
1143 be incorrectly associated with a different cache line. This false
1144 hazard might then cause a processor deadlock. The workaround enables
1145 the L1 caching of the NEON accesses and disables the PLD instruction
1146 in the ACTLR register. Note that setting specific bits in the ACTLR
1147 register may not be available in non-secure mode.
1149 config ARM_ERRATA_460075
1150 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1152 depends on !ARCH_MULTIPLATFORM
1154 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1155 erratum. Any asynchronous access to the L2 cache may encounter a
1156 situation in which recent store transactions to the L2 cache are lost
1157 and overwritten with stale memory contents from external memory. The
1158 workaround disables the write-allocate mode for the L2 cache via the
1159 ACTLR register. Note that setting specific bits in the ACTLR register
1160 may not be available in non-secure mode.
1162 config ARM_ERRATA_742230
1163 bool "ARM errata: DMB operation may be faulty"
1164 depends on CPU_V7 && SMP
1165 depends on !ARCH_MULTIPLATFORM
1167 This option enables the workaround for the 742230 Cortex-A9
1168 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1169 between two write operations may not ensure the correct visibility
1170 ordering of the two writes. This workaround sets a specific bit in
1171 the diagnostic register of the Cortex-A9 which causes the DMB
1172 instruction to behave as a DSB, ensuring the correct behaviour of
1175 config ARM_ERRATA_742231
1176 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1177 depends on CPU_V7 && SMP
1178 depends on !ARCH_MULTIPLATFORM
1180 This option enables the workaround for the 742231 Cortex-A9
1181 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1182 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1183 accessing some data located in the same cache line, may get corrupted
1184 data due to bad handling of the address hazard when the line gets
1185 replaced from one of the CPUs at the same time as another CPU is
1186 accessing it. This workaround sets specific bits in the diagnostic
1187 register of the Cortex-A9 which reduces the linefill issuing
1188 capabilities of the processor.
1190 config PL310_ERRATA_588369
1191 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1192 depends on CACHE_L2X0
1194 The PL310 L2 cache controller implements three types of Clean &
1195 Invalidate maintenance operations: by Physical Address
1196 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1197 They are architecturally defined to behave as the execution of a
1198 clean operation followed immediately by an invalidate operation,
1199 both performing to the same memory location. This functionality
1200 is not correctly implemented in PL310 as clean lines are not
1201 invalidated as a result of these operations.
1203 config ARM_ERRATA_643719
1204 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1205 depends on CPU_V7 && SMP
1207 This option enables the workaround for the 643719 Cortex-A9 (prior to
1208 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1209 register returns zero when it should return one. The workaround
1210 corrects this value, ensuring cache maintenance operations which use
1211 it behave as intended and avoiding data corruption.
1213 config ARM_ERRATA_720789
1214 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1217 This option enables the workaround for the 720789 Cortex-A9 (prior to
1218 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1219 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1220 As a consequence of this erratum, some TLB entries which should be
1221 invalidated are not, resulting in an incoherency in the system page
1222 tables. The workaround changes the TLB flushing routines to invalidate
1223 entries regardless of the ASID.
1225 config PL310_ERRATA_727915
1226 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1227 depends on CACHE_L2X0
1229 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1230 operation (offset 0x7FC). This operation runs in background so that
1231 PL310 can handle normal accesses while it is in progress. Under very
1232 rare circumstances, due to this erratum, write data can be lost when
1233 PL310 treats a cacheable write transaction during a Clean &
1234 Invalidate by Way operation.
1236 config ARM_ERRATA_743622
1237 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1239 depends on !ARCH_MULTIPLATFORM
1241 This option enables the workaround for the 743622 Cortex-A9
1242 (r2p*) erratum. Under very rare conditions, a faulty
1243 optimisation in the Cortex-A9 Store Buffer may lead to data
1244 corruption. This workaround sets a specific bit in the diagnostic
1245 register of the Cortex-A9 which disables the Store Buffer
1246 optimisation, preventing the defect from occurring. This has no
1247 visible impact on the overall performance or power consumption of the
1250 config ARM_ERRATA_751472
1251 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1253 depends on !ARCH_MULTIPLATFORM
1255 This option enables the workaround for the 751472 Cortex-A9 (prior
1256 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1257 completion of a following broadcasted operation if the second
1258 operation is received by a CPU before the ICIALLUIS has completed,
1259 potentially leading to corrupted entries in the cache or TLB.
1261 config PL310_ERRATA_753970
1262 bool "PL310 errata: cache sync operation may be faulty"
1263 depends on CACHE_PL310
1265 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1267 Under some condition the effect of cache sync operation on
1268 the store buffer still remains when the operation completes.
1269 This means that the store buffer is always asked to drain and
1270 this prevents it from merging any further writes. The workaround
1271 is to replace the normal offset of cache sync operation (0x730)
1272 by another offset targeting an unmapped PL310 register 0x740.
1273 This has the same effect as the cache sync operation: store buffer
1274 drain and waiting for all buffers empty.
1276 config ARM_ERRATA_754322
1277 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1280 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1281 r3p*) erratum. A speculative memory access may cause a page table walk
1282 which starts prior to an ASID switch but completes afterwards. This
1283 can populate the micro-TLB with a stale entry which may be hit with
1284 the new ASID. This workaround places two dsb instructions in the mm
1285 switching code so that no page table walks can cross the ASID switch.
1287 config ARM_ERRATA_754327
1288 bool "ARM errata: no automatic Store Buffer drain"
1289 depends on CPU_V7 && SMP
1291 This option enables the workaround for the 754327 Cortex-A9 (prior to
1292 r2p0) erratum. The Store Buffer does not have any automatic draining
1293 mechanism and therefore a livelock may occur if an external agent
1294 continuously polls a memory location waiting to observe an update.
1295 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1296 written polling loops from denying visibility of updates to memory.
1298 config ARM_ERRATA_364296
1299 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1302 This options enables the workaround for the 364296 ARM1136
1303 r0p2 erratum (possible cache data corruption with
1304 hit-under-miss enabled). It sets the undocumented bit 31 in
1305 the auxiliary control register and the FI bit in the control
1306 register, thus disabling hit-under-miss without putting the
1307 processor into full low interrupt latency mode. ARM11MPCore
1310 config ARM_ERRATA_764369
1311 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1312 depends on CPU_V7 && SMP
1314 This option enables the workaround for erratum 764369
1315 affecting Cortex-A9 MPCore with two or more processors (all
1316 current revisions). Under certain timing circumstances, a data
1317 cache line maintenance operation by MVA targeting an Inner
1318 Shareable memory region may fail to proceed up to either the
1319 Point of Coherency or to the Point of Unification of the
1320 system. This workaround adds a DSB instruction before the
1321 relevant cache maintenance functions and sets a specific bit
1322 in the diagnostic control register of the SCU.
1324 config PL310_ERRATA_769419
1325 bool "PL310 errata: no automatic Store Buffer drain"
1326 depends on CACHE_L2X0
1328 On revisions of the PL310 prior to r3p2, the Store Buffer does
1329 not automatically drain. This can cause normal, non-cacheable
1330 writes to be retained when the memory system is idle, leading
1331 to suboptimal I/O performance for drivers using coherent DMA.
1332 This option adds a write barrier to the cpu_idle loop so that,
1333 on systems with an outer cache, the store buffer is drained
1336 config ARM_ERRATA_775420
1337 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1340 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1341 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1342 operation aborts with MMU exception, it might cause the processor
1343 to deadlock. This workaround puts DSB before executing ISB if
1344 an abort may occur on cache maintenance.
1346 config ARM_ERRATA_798181
1347 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1348 depends on CPU_V7 && SMP
1350 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1351 adequately shooting down all use of the old entries. This
1352 option enables the Linux kernel workaround for this erratum
1353 which sends an IPI to the CPUs that are running the same ASID
1354 as the one being invalidated.
1356 config ARM_ERRATA_773022
1357 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1360 This option enables the workaround for the 773022 Cortex-A15
1361 (up to r0p4) erratum. In certain rare sequences of code, the
1362 loop buffer may deliver incorrect instructions. This
1363 workaround disables the loop buffer to avoid the erratum.
1367 source "arch/arm/common/Kconfig"
1377 Find out whether you have ISA slots on your motherboard. ISA is the
1378 name of a bus system, i.e. the way the CPU talks to the other stuff
1379 inside your box. Other bus systems are PCI, EISA, MicroChannel
1380 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1381 newer boards don't support it. If you have ISA, say Y, otherwise N.
1383 # Select ISA DMA controller support
1388 # Select ISA DMA interface
1393 bool "PCI support" if MIGHT_HAVE_PCI
1395 Find out whether you have a PCI motherboard. PCI is the name of a
1396 bus system, i.e. the way the CPU talks to the other stuff inside
1397 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1398 VESA. If you have PCI, say Y, otherwise N.
1404 config PCI_NANOENGINE
1405 bool "BSE nanoEngine PCI support"
1406 depends on SA1100_NANOENGINE
1408 Enable PCI on the BSE nanoEngine board.
1413 config PCI_HOST_ITE8152
1415 depends on PCI && MACH_ARMCORE
1419 source "drivers/pci/Kconfig"
1420 source "drivers/pci/pcie/Kconfig"
1422 source "drivers/pcmcia/Kconfig"
1426 menu "Kernel Features"
1431 This option should be selected by machines which have an SMP-
1434 The only effect of this option is to make the SMP-related
1435 options available to the user for configuration.
1438 bool "Symmetric Multi-Processing"
1439 depends on CPU_V6K || CPU_V7
1440 depends on GENERIC_CLOCKEVENTS
1442 depends on MMU || ARM_MPU
1444 This enables support for systems with more than one CPU. If you have
1445 a system with only one CPU, like most personal computers, say N. If
1446 you have a system with more than one CPU, say Y.
1448 If you say N here, the kernel will run on single and multiprocessor
1449 machines, but will use only one CPU of a multiprocessor machine. If
1450 you say Y here, the kernel will run on many, but not all, single
1451 processor machines. On a single processor machine, the kernel will
1452 run faster if you say N here.
1454 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1455 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1456 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1458 If you don't know what to do here, say N.
1461 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1462 depends on SMP && !XIP_KERNEL && MMU
1465 SMP kernels contain instructions which fail on non-SMP processors.
1466 Enabling this option allows the kernel to modify itself to make
1467 these instructions safe. Disabling it allows about 1K of space
1470 If you don't know what to do here, say Y.
1472 config ARM_CPU_TOPOLOGY
1473 bool "Support cpu topology definition"
1474 depends on SMP && CPU_V7
1477 Support ARM cpu topology definition. The MPIDR register defines
1478 affinity between processors which is then used to describe the cpu
1479 topology of an ARM System.
1482 bool "Multi-core scheduler support"
1483 depends on ARM_CPU_TOPOLOGY
1485 Multi-core scheduler support improves the CPU scheduler's decision
1486 making when dealing with multi-core CPU chips at a cost of slightly
1487 increased overhead in some places. If unsure say N here.
1490 bool "SMT scheduler support"
1491 depends on ARM_CPU_TOPOLOGY
1493 Improves the CPU scheduler's decision making when dealing with
1494 MultiThreading at a cost of slightly increased overhead in some
1495 places. If unsure say N here.
1500 This option enables support for the ARM system coherency unit
1502 config HAVE_ARM_ARCH_TIMER
1503 bool "Architected timer support"
1505 select ARM_ARCH_TIMER
1506 select GENERIC_CLOCKEVENTS
1508 This option enables support for the ARM architected timer
1513 select CLKSRC_OF if OF
1515 This options enables support for the ARM timer and watchdog unit
1518 bool "Multi-Cluster Power Management"
1519 depends on CPU_V7 && SMP
1521 This option provides the common power management infrastructure
1522 for (multi-)cluster based systems, such as big.LITTLE based
1526 bool "big.LITTLE support (Experimental)"
1527 depends on CPU_V7 && SMP
1530 This option enables support selections for the big.LITTLE
1531 system architecture.
1534 bool "big.LITTLE switcher support"
1535 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1537 select ARM_CPU_SUSPEND
1539 The big.LITTLE "switcher" provides the core functionality to
1540 transparently handle transition between a cluster of A15's
1541 and a cluster of A7's in a big.LITTLE system.
1543 config BL_SWITCHER_DUMMY_IF
1544 tristate "Simple big.LITTLE switcher user interface"
1545 depends on BL_SWITCHER && DEBUG_KERNEL
1547 This is a simple and dummy char dev interface to control
1548 the big.LITTLE switcher core code. It is meant for
1549 debugging purposes only.
1552 prompt "Memory split"
1555 Select the desired split between kernel and user memory.
1557 If you are not absolutely sure what you are doing, leave this
1561 bool "3G/1G user/kernel split"
1563 bool "2G/2G user/kernel split"
1565 bool "1G/3G user/kernel split"
1570 default 0x40000000 if VMSPLIT_1G
1571 default 0x80000000 if VMSPLIT_2G
1575 int "Maximum number of CPUs (2-32)"
1581 bool "Support for hot-pluggable CPUs"
1584 Say Y here to experiment with turning CPUs off and on. CPUs
1585 can be controlled through /sys/devices/system/cpu.
1588 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1591 Say Y here if you want Linux to communicate with system firmware
1592 implementing the PSCI specification for CPU-centric power
1593 management operations described in ARM document number ARM DEN
1594 0022A ("Power State Coordination Interface System Software on
1597 # The GPIO number here must be sorted by descending number. In case of
1598 # a multiplatform kernel, we just want the highest value required by the
1599 # selected platforms.
1602 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1603 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1604 default 392 if ARCH_U8500
1605 default 352 if ARCH_VT8500
1606 default 288 if ARCH_SUNXI
1607 default 264 if MACH_H4700
1610 Maximum number of GPIOs in the system.
1612 If unsure, leave the default value.
1614 source kernel/Kconfig.preempt
1618 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1619 ARCH_S5PV210 || ARCH_EXYNOS4
1620 default AT91_TIMER_HZ if ARCH_AT91
1621 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1625 depends on HZ_FIXED = 0
1626 prompt "Timer frequency"
1650 default HZ_FIXED if HZ_FIXED != 0
1651 default 100 if HZ_100
1652 default 200 if HZ_200
1653 default 250 if HZ_250
1654 default 300 if HZ_300
1655 default 500 if HZ_500
1659 def_bool HIGH_RES_TIMERS
1662 def_bool HIGH_RES_TIMERS
1664 config THUMB2_KERNEL
1665 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1666 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1667 default y if CPU_THUMBONLY
1669 select ARM_ASM_UNIFIED
1672 By enabling this option, the kernel will be compiled in
1673 Thumb-2 mode. A compiler/assembler that understand the unified
1674 ARM-Thumb syntax is needed.
1678 config THUMB2_AVOID_R_ARM_THM_JUMP11
1679 bool "Work around buggy Thumb-2 short branch relocations in gas"
1680 depends on THUMB2_KERNEL && MODULES
1683 Various binutils versions can resolve Thumb-2 branches to
1684 locally-defined, preemptible global symbols as short-range "b.n"
1685 branch instructions.
1687 This is a problem, because there's no guarantee the final
1688 destination of the symbol, or any candidate locations for a
1689 trampoline, are within range of the branch. For this reason, the
1690 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1691 relocation in modules at all, and it makes little sense to add
1694 The symptom is that the kernel fails with an "unsupported
1695 relocation" error when loading some modules.
1697 Until fixed tools are available, passing
1698 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1699 code which hits this problem, at the cost of a bit of extra runtime
1700 stack usage in some cases.
1702 The problem is described in more detail at:
1703 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1705 Only Thumb-2 kernels are affected.
1707 Unless you are sure your tools don't have this problem, say Y.
1709 config ARM_ASM_UNIFIED
1713 bool "Use the ARM EABI to compile the kernel"
1715 This option allows for the kernel to be compiled using the latest
1716 ARM ABI (aka EABI). This is only useful if you are using a user
1717 space environment that is also compiled with EABI.
1719 Since there are major incompatibilities between the legacy ABI and
1720 EABI, especially with regard to structure member alignment, this
1721 option also changes the kernel syscall calling convention to
1722 disambiguate both ABIs and allow for backward compatibility support
1723 (selected with CONFIG_OABI_COMPAT).
1725 To use this you need GCC version 4.0.0 or later.
1728 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1729 depends on AEABI && !THUMB2_KERNEL
1731 This option preserves the old syscall interface along with the
1732 new (ARM EABI) one. It also provides a compatibility layer to
1733 intercept syscalls that have structure arguments which layout
1734 in memory differs between the legacy ABI and the new ARM EABI
1735 (only for non "thumb" binaries). This option adds a tiny
1736 overhead to all syscalls and produces a slightly larger kernel.
1738 The seccomp filter system will not be available when this is
1739 selected, since there is no way yet to sensibly distinguish
1740 between calling conventions during filtering.
1742 If you know you'll be using only pure EABI user space then you
1743 can say N here. If this option is not selected and you attempt
1744 to execute a legacy ABI binary then the result will be
1745 UNPREDICTABLE (in fact it can be predicted that it won't work
1746 at all). If in doubt say N.
1748 config ARCH_HAS_HOLES_MEMORYMODEL
1751 config ARCH_SPARSEMEM_ENABLE
1754 config ARCH_SPARSEMEM_DEFAULT
1755 def_bool ARCH_SPARSEMEM_ENABLE
1757 config ARCH_SELECT_MEMORY_MODEL
1758 def_bool ARCH_SPARSEMEM_ENABLE
1760 config HAVE_ARCH_PFN_VALID
1761 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1764 bool "High Memory Support"
1767 The address space of ARM processors is only 4 Gigabytes large
1768 and it has to accommodate user address space, kernel address
1769 space as well as some memory mapped IO. That means that, if you
1770 have a large amount of physical memory and/or IO, not all of the
1771 memory can be "permanently mapped" by the kernel. The physical
1772 memory that is not permanently mapped is called "high memory".
1774 Depending on the selected kernel/user memory split, minimum
1775 vmalloc space and actual amount of RAM, you may not need this
1776 option which should result in a slightly faster kernel.
1781 bool "Allocate 2nd-level pagetables from highmem"
1784 config HW_PERF_EVENTS
1785 bool "Enable hardware performance counter support for perf events"
1786 depends on PERF_EVENTS
1789 Enable hardware performance counter support for perf events. If
1790 disabled, perf events will use software events only.
1792 config SYS_SUPPORTS_HUGETLBFS
1796 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1800 config ARCH_WANT_GENERAL_HUGETLB
1805 config FORCE_MAX_ZONEORDER
1806 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1807 range 11 64 if ARCH_SHMOBILE_LEGACY
1808 default "12" if SOC_AM33XX
1809 default "9" if SA1111
1812 The kernel memory allocator divides physically contiguous memory
1813 blocks into "zones", where each zone is a power of two number of
1814 pages. This option selects the largest power of two that the kernel
1815 keeps in the memory allocator. If you need to allocate very large
1816 blocks of physically contiguous memory, then you may need to
1817 increase this value.
1819 This config option is actually maximum order plus one. For example,
1820 a value of 11 means that the largest free memory block is 2^10 pages.
1822 config ALIGNMENT_TRAP
1824 depends on CPU_CP15_MMU
1825 default y if !ARCH_EBSA110
1826 select HAVE_PROC_CPU if PROC_FS
1828 ARM processors cannot fetch/store information which is not
1829 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1830 address divisible by 4. On 32-bit ARM processors, these non-aligned
1831 fetch/store instructions will be emulated in software if you say
1832 here, which has a severe performance impact. This is necessary for
1833 correct operation of some network protocols. With an IP-only
1834 configuration it is safe to say N, otherwise say Y.
1836 config UACCESS_WITH_MEMCPY
1837 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1839 default y if CPU_FEROCEON
1841 Implement faster copy_to_user and clear_user methods for CPU
1842 cores where a 8-word STM instruction give significantly higher
1843 memory write throughput than a sequence of individual 32bit stores.
1845 A possible side effect is a slight increase in scheduling latency
1846 between threads sharing the same address space if they invoke
1847 such copy operations with large buffers.
1849 However, if the CPU data cache is using a write-allocate mode,
1850 this option is unlikely to provide any performance gain.
1854 prompt "Enable seccomp to safely compute untrusted bytecode"
1856 This kernel feature is useful for number crunching applications
1857 that may need to compute untrusted bytecode during their
1858 execution. By using pipes or other transports made available to
1859 the process as file descriptors supporting the read/write
1860 syscalls, it's possible to isolate those applications in
1861 their own address space using seccomp. Once seccomp is
1862 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1863 and the task is only allowed to execute a few safe syscalls
1864 defined by each seccomp mode.
1866 config CC_STACKPROTECTOR
1867 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1869 This option turns on the -fstack-protector GCC feature. This
1870 feature puts, at the beginning of functions, a canary value on
1871 the stack just before the return address, and validates
1872 the value just before actually returning. Stack based buffer
1873 overflows (that need to overwrite this return address) now also
1874 overwrite the canary, which gets detected and the attack is then
1875 neutralized via a kernel panic.
1876 This feature requires gcc version 4.2 or above.
1889 bool "Xen guest support on ARM (EXPERIMENTAL)"
1890 depends on ARM && AEABI && OF
1891 depends on CPU_V7 && !CPU_V6
1892 depends on !GENERIC_ATOMIC64
1896 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1903 bool "Flattened Device Tree support"
1906 select OF_EARLY_FLATTREE
1908 Include support for flattened device tree machine descriptions.
1911 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1914 This is the traditional way of passing data to the kernel at boot
1915 time. If you are solely relying on the flattened device tree (or
1916 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1917 to remove ATAGS support from your kernel binary. If unsure,
1920 config DEPRECATED_PARAM_STRUCT
1921 bool "Provide old way to pass kernel parameters"
1924 This was deprecated in 2001 and announced to live on for 5 years.
1925 Some old boot loaders still use this way.
1927 # Compressed boot loader in ROM. Yes, we really want to ask about
1928 # TEXT and BSS so we preserve their values in the config files.
1929 config ZBOOT_ROM_TEXT
1930 hex "Compressed ROM boot loader base address"
1933 The physical address at which the ROM-able zImage is to be
1934 placed in the target. Platforms which normally make use of
1935 ROM-able zImage formats normally set this to a suitable
1936 value in their defconfig file.
1938 If ZBOOT_ROM is not enabled, this has no effect.
1940 config ZBOOT_ROM_BSS
1941 hex "Compressed ROM boot loader BSS address"
1944 The base address of an area of read/write memory in the target
1945 for the ROM-able zImage which must be available while the
1946 decompressor is running. It must be large enough to hold the
1947 entire decompressed kernel plus an additional 128 KiB.
1948 Platforms which normally make use of ROM-able zImage formats
1949 normally set this to a suitable value in their defconfig file.
1951 If ZBOOT_ROM is not enabled, this has no effect.
1954 bool "Compressed boot loader in ROM/flash"
1955 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1957 Say Y here if you intend to execute your compressed kernel image
1958 (zImage) directly from ROM or flash. If unsure, say N.
1961 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1962 depends on ZBOOT_ROM && ARCH_SH7372
1963 default ZBOOT_ROM_NONE
1965 Include experimental SD/MMC loading code in the ROM-able zImage.
1966 With this enabled it is possible to write the ROM-able zImage
1967 kernel image to an MMC or SD card and boot the kernel straight
1968 from the reset vector. At reset the processor Mask ROM will load
1969 the first part of the ROM-able zImage which in turn loads the
1970 rest the kernel image to RAM.
1972 config ZBOOT_ROM_NONE
1973 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1975 Do not load image from SD or MMC
1977 config ZBOOT_ROM_MMCIF
1978 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1980 Load image from MMCIF hardware block.
1982 config ZBOOT_ROM_SH_MOBILE_SDHI
1983 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1985 Load image from SDHI hardware block
1989 config ARM_APPENDED_DTB
1990 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1991 depends on OF && !ZBOOT_ROM
1993 With this option, the boot code will look for a device tree binary
1994 (DTB) appended to zImage
1995 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1997 This is meant as a backward compatibility convenience for those
1998 systems with a bootloader that can't be upgraded to accommodate
1999 the documented boot protocol using a device tree.
2001 Beware that there is very little in terms of protection against
2002 this option being confused by leftover garbage in memory that might
2003 look like a DTB header after a reboot if no actual DTB is appended
2004 to zImage. Do not leave this option active in a production kernel
2005 if you don't intend to always append a DTB. Proper passing of the
2006 location into r2 of a bootloader provided DTB is always preferable
2009 config ARM_ATAG_DTB_COMPAT
2010 bool "Supplement the appended DTB with traditional ATAG information"
2011 depends on ARM_APPENDED_DTB
2013 Some old bootloaders can't be updated to a DTB capable one, yet
2014 they provide ATAGs with memory configuration, the ramdisk address,
2015 the kernel cmdline string, etc. Such information is dynamically
2016 provided by the bootloader and can't always be stored in a static
2017 DTB. To allow a device tree enabled kernel to be used with such
2018 bootloaders, this option allows zImage to extract the information
2019 from the ATAG list and store it at run time into the appended DTB.
2022 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2023 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2025 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2026 bool "Use bootloader kernel arguments if available"
2028 Uses the command-line options passed by the boot loader instead of
2029 the device tree bootargs property. If the boot loader doesn't provide
2030 any, the device tree bootargs property will be used.
2032 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2033 bool "Extend with bootloader kernel arguments"
2035 The command-line arguments provided by the boot loader will be
2036 appended to the the device tree bootargs property.
2041 string "Default kernel command string"
2044 On some architectures (EBSA110 and CATS), there is currently no way
2045 for the boot loader to pass arguments to the kernel. For these
2046 architectures, you should supply some command-line options at build
2047 time by entering them here. As a minimum, you should specify the
2048 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2051 prompt "Kernel command line type" if CMDLINE != ""
2052 default CMDLINE_FROM_BOOTLOADER
2055 config CMDLINE_FROM_BOOTLOADER
2056 bool "Use bootloader kernel arguments if available"
2058 Uses the command-line options passed by the boot loader. If
2059 the boot loader doesn't provide any, the default kernel command
2060 string provided in CMDLINE will be used.
2062 config CMDLINE_EXTEND
2063 bool "Extend bootloader kernel arguments"
2065 The command-line arguments provided by the boot loader will be
2066 appended to the default kernel command string.
2068 config CMDLINE_FORCE
2069 bool "Always use the default kernel command string"
2071 Always use the default kernel command string, even if the boot
2072 loader passes other arguments to the kernel.
2073 This is useful if you cannot or don't want to change the
2074 command-line options your boot loader passes to the kernel.
2078 bool "Kernel Execute-In-Place from ROM"
2079 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2081 Execute-In-Place allows the kernel to run from non-volatile storage
2082 directly addressable by the CPU, such as NOR flash. This saves RAM
2083 space since the text section of the kernel is not loaded from flash
2084 to RAM. Read-write sections, such as the data section and stack,
2085 are still copied to RAM. The XIP kernel is not compressed since
2086 it has to run directly from flash, so it will take more space to
2087 store it. The flash address used to link the kernel object files,
2088 and for storing it, is configuration dependent. Therefore, if you
2089 say Y here, you must know the proper physical address where to
2090 store the kernel image depending on your own flash memory usage.
2092 Also note that the make target becomes "make xipImage" rather than
2093 "make zImage" or "make Image". The final kernel binary to put in
2094 ROM memory will be arch/arm/boot/xipImage.
2098 config XIP_PHYS_ADDR
2099 hex "XIP Kernel Physical Location"
2100 depends on XIP_KERNEL
2101 default "0x00080000"
2103 This is the physical address in your flash memory the kernel will
2104 be linked for and stored to. This address is dependent on your
2108 bool "Kexec system call (EXPERIMENTAL)"
2109 depends on (!SMP || PM_SLEEP_SMP)
2111 kexec is a system call that implements the ability to shutdown your
2112 current kernel, and to start another kernel. It is like a reboot
2113 but it is independent of the system firmware. And like a reboot
2114 you can start any kernel with it, not just Linux.
2116 It is an ongoing process to be certain the hardware in a machine
2117 is properly shutdown, so do not be surprised if this code does not
2118 initially work for you.
2121 bool "Export atags in procfs"
2122 depends on ATAGS && KEXEC
2125 Should the atags used to boot the kernel be exported in an "atags"
2126 file in procfs. Useful with kexec.
2129 bool "Build kdump crash kernel (EXPERIMENTAL)"
2131 Generate crash dump after being started by kexec. This should
2132 be normally only set in special crash dump kernels which are
2133 loaded in the main kernel with kexec-tools into a specially
2134 reserved region and then later executed after a crash by
2135 kdump/kexec. The crash dump kernel must be compiled to a
2136 memory address not used by the main kernel
2138 For more details see Documentation/kdump/kdump.txt
2140 config AUTO_ZRELADDR
2141 bool "Auto calculation of the decompressed kernel image address"
2142 depends on !ZBOOT_ROM
2144 ZRELADDR is the physical address where the decompressed kernel
2145 image will be placed. If AUTO_ZRELADDR is selected, the address
2146 will be determined at run-time by masking the current IP with
2147 0xf8000000. This assumes the zImage being placed in the first 128MB
2148 from start of memory.
2152 menu "CPU Power Management"
2155 source "drivers/cpufreq/Kconfig"
2158 source "drivers/cpuidle/Kconfig"
2162 menu "Floating point emulation"
2164 comment "At least one emulation must be selected"
2167 bool "NWFPE math emulation"
2168 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2170 Say Y to include the NWFPE floating point emulator in the kernel.
2171 This is necessary to run most binaries. Linux does not currently
2172 support floating point hardware so you need to say Y here even if
2173 your machine has an FPA or floating point co-processor podule.
2175 You may say N here if you are going to load the Acorn FPEmulator
2176 early in the bootup.
2179 bool "Support extended precision"
2180 depends on FPE_NWFPE
2182 Say Y to include 80-bit support in the kernel floating-point
2183 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2184 Note that gcc does not generate 80-bit operations by default,
2185 so in most cases this option only enlarges the size of the
2186 floating point emulator without any good reason.
2188 You almost surely want to say N here.
2191 bool "FastFPE math emulation (EXPERIMENTAL)"
2192 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2194 Say Y here to include the FAST floating point emulator in the kernel.
2195 This is an experimental much faster emulator which now also has full
2196 precision for the mantissa. It does not support any exceptions.
2197 It is very simple, and approximately 3-6 times faster than NWFPE.
2199 It should be sufficient for most programs. It may be not suitable
2200 for scientific calculations, but you have to check this for yourself.
2201 If you do not feel you need a faster FP emulation you should better
2205 bool "VFP-format floating point maths"
2206 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2208 Say Y to include VFP support code in the kernel. This is needed
2209 if your hardware includes a VFP unit.
2211 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2212 release notes and additional status information.
2214 Say N if your target does not have VFP hardware.
2222 bool "Advanced SIMD (NEON) Extension support"
2223 depends on VFPv3 && CPU_V7
2225 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2228 config KERNEL_MODE_NEON
2229 bool "Support for NEON in kernel mode"
2230 depends on NEON && AEABI
2232 Say Y to include support for NEON in kernel mode.
2236 menu "Userspace binary formats"
2238 source "fs/Kconfig.binfmt"
2241 tristate "RISC OS personality"
2244 Say Y here to include the kernel code necessary if you want to run
2245 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2246 experimental; if this sounds frightening, say N and sleep in peace.
2247 You can also say M here to compile this support as a module (which
2248 will be called arthur).
2252 menu "Power management options"
2254 source "kernel/power/Kconfig"
2256 config ARCH_SUSPEND_POSSIBLE
2257 depends on !ARCH_S5PC100
2258 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2259 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2262 config ARM_CPU_SUSPEND
2267 source "net/Kconfig"
2269 source "drivers/Kconfig"
2273 source "arch/arm/Kconfig.debug"
2275 source "security/Kconfig"
2277 source "crypto/Kconfig"
2279 source "lib/Kconfig"
2281 source "arch/arm/kvm/Kconfig"