4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
39 select HAVE_KERNEL_GZIP
40 select HAVE_KERNEL_LZMA
41 select HAVE_KERNEL_LZO
43 select HAVE_KPROBES if !XIP_KERNEL
44 select HAVE_KRETPROBES if (HAVE_KPROBES)
46 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
47 select HAVE_PERF_EVENTS
48 select HAVE_REGS_AND_STACK_ACCESS_API
49 select HAVE_SYSCALL_TRACEPOINTS
52 select PERF_USE_VMALLOC
54 select SYS_SUPPORTS_APM_EMULATION
55 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
56 select MODULES_USE_ELF_REL
57 select CLONE_BACKWARDS
59 The ARM series is a line of low-power-consumption RISC chip designs
60 licensed by ARM Ltd and targeted at embedded applications and
61 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
62 manufactured, but legacy ARM-based PC hardware remains popular in
63 Europe. There is an ARM Linux project with a web page at
64 <http://www.arm.linux.org.uk/>.
66 config ARM_HAS_SG_CHAIN
69 config NEED_SG_DMA_LENGTH
72 config ARM_DMA_USE_IOMMU
74 select ARM_HAS_SG_CHAIN
75 select NEED_SG_DMA_LENGTH
83 config SYS_SUPPORTS_APM_EMULATION
91 select GENERIC_ALLOCATOR
102 The Extended Industry Standard Architecture (EISA) bus was
103 developed as an open alternative to the IBM MicroChannel bus.
105 The EISA bus provided some of the features of the IBM MicroChannel
106 bus while maintaining backward compatibility with cards made for
107 the older ISA bus. The EISA bus saw limited use between 1988 and
108 1995 when it was made obsolete by the PCI bus.
110 Say Y here if you are building a kernel for an EISA-based machine.
117 config STACKTRACE_SUPPORT
121 config HAVE_LATENCYTOP_SUPPORT
126 config LOCKDEP_SUPPORT
130 config TRACE_IRQFLAGS_SUPPORT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config GENERIC_HWEIGHT
158 config GENERIC_CALIBRATE_DELAY
162 config ARCH_MAY_HAVE_PC_FDC
168 config NEED_DMA_MAP_STATE
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
174 config GENERIC_ISA_DMA
180 config NEED_RET_TO_USER
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_GPIO_H
214 Select this when mach/gpio.h is required to provide special
215 definitions for this platform. The need for mach/gpio.h should
216 be avoided when possible.
218 config NEED_MACH_IO_H
221 Select this when mach/io.h is required to provide special
222 definitions for this platform. The need for mach/io.h should
223 be avoided when possible.
225 config NEED_MACH_MEMORY_H
228 Select this when mach/memory.h is required to provide special
229 definitions for this platform. The need for mach/memory.h should
230 be avoided when possible.
233 hex "Physical address of main memory" if MMU
234 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
235 default DRAM_BASE if !MMU
237 Please provide the physical address corresponding to the
238 location of main memory in your system.
244 source "init/Kconfig"
246 source "kernel/Kconfig.freezer"
251 bool "MMU-based Paged Memory Management Support"
254 Select if you want MMU-based virtualised addressing space
255 support by paged memory management. If unsure, say 'Y'.
258 # The "ARM system type" choice list is ordered alphabetically by option
259 # text. Please add new entries in the option alphabetic order.
262 prompt "ARM system type"
263 default ARCH_VERSATILE if !MMU
264 default ARCH_MULTIPLATFORM if MMU
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
269 select ARM_PATCH_PHYS_VIRT
272 select MULTI_IRQ_HANDLER
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
289 select VERSATILE_FPGA_IRQ
291 Support for ARM's Integrator platform.
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select ARM_TIMER_SP804
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select VERSATILE_FPGA_IRQ
324 This enables support for ARM Ltd Versatile board.
328 select ARCH_REQUIRE_GPIOLIB
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
335 select PINCTRL_AT91 if USE_OF
337 This enables support for systems based on Atmel
338 AT91RM9200 and AT91SAM9* processors.
341 bool "Broadcom BCM2835 family"
342 select ARCH_REQUIRE_GPIOLIB
344 select ARM_ERRATA_411920
345 select ARM_TIMER_SP804
350 select GENERIC_CLOCKEVENTS
351 select MULTI_IRQ_HANDLER
353 select PINCTRL_BCM2835
357 This enables support for the Broadcom BCM2835 SoC. This SoC is
358 use in the Raspberry Pi, and Roku 2 devices.
361 bool "Cavium Networks CNS3XXX family"
364 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_CACHE_L2X0
366 select MIGHT_HAVE_PCI
367 select PCI_DOMAINS if PCI
369 Support for Cavium Networks CNS3XXX platform.
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
379 select MULTI_IRQ_HANDLER
380 select NEED_MACH_MEMORY_H
383 Support for Cirrus Logic 711x/721x/731x based boards.
386 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
391 Support for the Cortina Systems Gemini family SoCs
395 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
405 Support for CSR SiRFprimaII/Marco/Polo platforms
409 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_REQUIRE_GPIOLIB
425 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H if !MMU
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Freescale MXS-based"
448 select ARCH_REQUIRE_GPIOLIB
452 select GENERIC_CLOCKEVENTS
453 select HAVE_CLK_PREPARE
454 select MULTI_IRQ_HANDLER
459 Support for Freescale MXS-based family of processors
462 bool "Hilscher NetX based"
466 select GENERIC_CLOCKEVENTS
468 This enables support for systems based on the Hilscher NetX Soc
471 bool "Hynix HMS720x-based"
472 select ARCH_USES_GETTIMEOFFSET
476 This enables support for systems based on the Hynix HMS720x
481 select ARCH_SUPPORTS_MSI
483 select NEED_MACH_MEMORY_H
484 select NEED_RET_TO_USER
489 Support for Intel's IOP13XX (XScale) family of processors.
494 select ARCH_REQUIRE_GPIOLIB
496 select NEED_MACH_GPIO_H
497 select NEED_RET_TO_USER
501 Support for Intel's 80219 and IOP32X (XScale) family of
507 select ARCH_REQUIRE_GPIOLIB
509 select NEED_MACH_GPIO_H
510 select NEED_RET_TO_USER
514 Support for Intel's IOP33X (XScale) family of processors.
519 select ARCH_HAS_DMA_SET_COHERENT_MASK
520 select ARCH_REQUIRE_GPIOLIB
523 select DMABOUNCE if PCI
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
526 select NEED_MACH_IO_H
528 Support for Intel's IXP4XX (XScale) family of processors.
532 select ARCH_REQUIRE_GPIOLIB
533 select COMMON_CLK_DOVE
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 select PLAT_ORION_LEGACY
566 Support for the following Marvell MV78xx0 series SoCs:
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
576 select PLAT_ORION_LEGACY
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
583 bool "Marvell PXA168/910/MMP2"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
591 select NEED_MACH_GPIO_H
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
635 select USB_ARCH_HAS_OHCI
638 Support for the NXP LPC32XX family of processors
642 select ARCH_HAS_CPUFREQ
647 select GENERIC_CLOCKEVENTS
650 select MIGHT_HAVE_CACHE_L2X0
654 This enables support for NVIDIA Tegra based systems (Tegra APX,
655 Tegra 6xx and Tegra 2 series).
658 bool "PXA2xx/PXA3xx-based"
660 select ARCH_HAS_CPUFREQ
662 select ARCH_REQUIRE_GPIOLIB
663 select ARM_CPU_SUSPEND if PM
667 select GENERIC_CLOCKEVENTS
670 select MULTI_IRQ_HANDLER
671 select NEED_MACH_GPIO_H
675 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
679 select ARCH_REQUIRE_GPIOLIB
681 select GENERIC_CLOCKEVENTS
684 Support for Qualcomm MSM/QSD based systems. This runs on the
685 apps processor of the MSM/QSD and depends on a shared memory
686 interface to the modem processor which runs the baseband
687 stack and controls some vital subsystems
688 (clock and power control, etc).
691 bool "Renesas SH-Mobile / R-Mobile"
693 select GENERIC_CLOCKEVENTS
695 select HAVE_MACH_CLKDEV
697 select MIGHT_HAVE_CACHE_L2X0
698 select MULTI_IRQ_HANDLER
699 select NEED_MACH_MEMORY_H
702 select PM_GENERIC_DOMAINS if PM
705 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
710 select ARCH_MAY_HAVE_PC_FDC
711 select ARCH_SPARSEMEM_ENABLE
712 select ARCH_USES_GETTIMEOFFSET
715 select HAVE_PATA_PLATFORM
717 select NEED_MACH_IO_H
718 select NEED_MACH_MEMORY_H
721 On the Acorn Risc-PC, Linux can support the internal IDE disk and
722 CD-ROM interface, serial and parallel port, and the floppy drive.
726 select ARCH_HAS_CPUFREQ
728 select ARCH_REQUIRE_GPIOLIB
729 select ARCH_SPARSEMEM_ENABLE
734 select GENERIC_CLOCKEVENTS
737 select NEED_MACH_GPIO_H
738 select NEED_MACH_MEMORY_H
741 Support for StrongARM 11x0 based boards.
744 bool "Samsung S3C24XX SoCs"
745 select ARCH_HAS_CPUFREQ
746 select ARCH_USES_GETTIMEOFFSET
749 select HAVE_S3C2410_I2C if I2C
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select HAVE_S3C_RTC if RTC_CLASS
752 select NEED_MACH_GPIO_H
753 select NEED_MACH_IO_H
755 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
756 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
757 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
758 Samsung SMDK2410 development board (and derivatives).
761 bool "Samsung S3C64XX"
762 select ARCH_HAS_CPUFREQ
763 select ARCH_REQUIRE_GPIOLIB
764 select ARCH_USES_GETTIMEOFFSET
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select NEED_MACH_GPIO_H
776 select S3C_GPIO_TRACK
777 select SAMSUNG_CLKSRC
778 select SAMSUNG_GPIOLIB_4BIT
779 select SAMSUNG_IRQ_VIC_TIMER
780 select USB_ARCH_HAS_OHCI
782 Samsung S3C64XX series based systems
785 bool "Samsung S5P6440 S5P6450"
789 select GENERIC_CLOCKEVENTS
791 select HAVE_S3C2410_I2C if I2C
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 select HAVE_S3C_RTC if RTC_CLASS
794 select NEED_MACH_GPIO_H
796 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
800 bool "Samsung S5PC100"
801 select ARCH_USES_GETTIMEOFFSET
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C2410_WATCHDOG if WATCHDOG
807 select HAVE_S3C_RTC if RTC_CLASS
808 select NEED_MACH_GPIO_H
810 Samsung S5PC100 series based systems
813 bool "Samsung S5PV210/S5PC110"
814 select ARCH_HAS_CPUFREQ
815 select ARCH_HAS_HOLES_MEMORYMODEL
816 select ARCH_SPARSEMEM_ENABLE
820 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_GPIO_H
826 select NEED_MACH_MEMORY_H
828 Samsung S5PV210/S5PC110 series based systems
831 bool "Samsung EXYNOS"
832 select ARCH_HAS_CPUFREQ
833 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARCH_SPARSEMEM_ENABLE
837 select GENERIC_CLOCKEVENTS
839 select HAVE_S3C2410_I2C if I2C
840 select HAVE_S3C2410_WATCHDOG if WATCHDOG
841 select HAVE_S3C_RTC if RTC_CLASS
842 select NEED_MACH_GPIO_H
843 select NEED_MACH_MEMORY_H
845 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
849 select ARCH_USES_GETTIMEOFFSET
853 select NEED_MACH_MEMORY_H
857 Support for the StrongARM based Digital DNARD machine, also known
858 as "Shark" (<http://www.shark-linux.de/shark.html>).
861 bool "ST-Ericsson U300 Series"
863 select ARCH_REQUIRE_GPIOLIB
865 select ARM_PATCH_PHYS_VIRT
871 select GENERIC_CLOCKEVENTS
875 Support for ST-Ericsson U300 series mobile platforms.
878 bool "ST-Ericsson U8500 Series"
880 select ARCH_HAS_CPUFREQ
881 select ARCH_REQUIRE_GPIOLIB
885 select GENERIC_CLOCKEVENTS
887 select MIGHT_HAVE_CACHE_L2X0
890 Support for ST-Ericsson's Ux500 architecture
893 bool "STMicroelectronics Nomadik"
894 select ARCH_REQUIRE_GPIOLIB
899 select GENERIC_CLOCKEVENTS
900 select MIGHT_HAVE_CACHE_L2X0
902 select PINCTRL_STN8815
905 Support for the Nomadik platform by ST-Ericsson
909 select ARCH_HAS_CPUFREQ
910 select ARCH_REQUIRE_GPIOLIB
915 select GENERIC_CLOCKEVENTS
918 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
922 select ARCH_HAS_HOLES_MEMORYMODEL
923 select ARCH_REQUIRE_GPIOLIB
925 select GENERIC_ALLOCATOR
926 select GENERIC_CLOCKEVENTS
927 select GENERIC_IRQ_CHIP
929 select NEED_MACH_GPIO_H
933 Support for TI's DaVinci platform.
938 select ARCH_HAS_CPUFREQ
939 select ARCH_HAS_HOLES_MEMORYMODEL
941 select ARCH_REQUIRE_GPIOLIB
944 select GENERIC_CLOCKEVENTS
945 select GENERIC_IRQ_CHIP
949 select NEED_MACH_IO_H if PCCARD
950 select NEED_MACH_MEMORY_H
952 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
956 menu "Multiple platform selection"
957 depends on ARCH_MULTIPLATFORM
959 comment "CPU Core family selection"
962 bool "ARMv4 based platforms (FA526, StrongARM)"
963 depends on !ARCH_MULTI_V6_V7
964 select ARCH_MULTI_V4_V5
966 config ARCH_MULTI_V4T
967 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
968 depends on !ARCH_MULTI_V6_V7
969 select ARCH_MULTI_V4_V5
972 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
973 depends on !ARCH_MULTI_V6_V7
974 select ARCH_MULTI_V4_V5
976 config ARCH_MULTI_V4_V5
980 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
981 select ARCH_MULTI_V6_V7
985 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
987 select ARCH_MULTI_V6_V7
991 config ARCH_MULTI_V6_V7
994 config ARCH_MULTI_CPU_AUTO
995 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1001 # This is sorted alphabetically by mach-* pathname. However, plat-*
1002 # Kconfigs may be included either alphabetically (according to the
1003 # plat- suffix) or along side the corresponding mach-* source.
1005 source "arch/arm/mach-mvebu/Kconfig"
1007 source "arch/arm/mach-at91/Kconfig"
1009 source "arch/arm/mach-bcm/Kconfig"
1011 source "arch/arm/mach-clps711x/Kconfig"
1013 source "arch/arm/mach-cns3xxx/Kconfig"
1015 source "arch/arm/mach-davinci/Kconfig"
1017 source "arch/arm/mach-dove/Kconfig"
1019 source "arch/arm/mach-ep93xx/Kconfig"
1021 source "arch/arm/mach-footbridge/Kconfig"
1023 source "arch/arm/mach-gemini/Kconfig"
1025 source "arch/arm/mach-h720x/Kconfig"
1027 source "arch/arm/mach-highbank/Kconfig"
1029 source "arch/arm/mach-integrator/Kconfig"
1031 source "arch/arm/mach-iop32x/Kconfig"
1033 source "arch/arm/mach-iop33x/Kconfig"
1035 source "arch/arm/mach-iop13xx/Kconfig"
1037 source "arch/arm/mach-ixp4xx/Kconfig"
1039 source "arch/arm/mach-kirkwood/Kconfig"
1041 source "arch/arm/mach-ks8695/Kconfig"
1043 source "arch/arm/mach-msm/Kconfig"
1045 source "arch/arm/mach-mv78xx0/Kconfig"
1047 source "arch/arm/mach-imx/Kconfig"
1049 source "arch/arm/mach-mxs/Kconfig"
1051 source "arch/arm/mach-netx/Kconfig"
1053 source "arch/arm/mach-nomadik/Kconfig"
1055 source "arch/arm/plat-omap/Kconfig"
1057 source "arch/arm/mach-omap1/Kconfig"
1059 source "arch/arm/mach-omap2/Kconfig"
1061 source "arch/arm/mach-orion5x/Kconfig"
1063 source "arch/arm/mach-picoxcell/Kconfig"
1065 source "arch/arm/mach-pxa/Kconfig"
1066 source "arch/arm/plat-pxa/Kconfig"
1068 source "arch/arm/mach-mmp/Kconfig"
1070 source "arch/arm/mach-realview/Kconfig"
1072 source "arch/arm/mach-sa1100/Kconfig"
1074 source "arch/arm/plat-samsung/Kconfig"
1076 source "arch/arm/mach-socfpga/Kconfig"
1078 source "arch/arm/plat-spear/Kconfig"
1080 source "arch/arm/mach-s3c24xx/Kconfig"
1083 source "arch/arm/mach-s3c64xx/Kconfig"
1086 source "arch/arm/mach-s5p64x0/Kconfig"
1088 source "arch/arm/mach-s5pc100/Kconfig"
1090 source "arch/arm/mach-s5pv210/Kconfig"
1092 source "arch/arm/mach-exynos/Kconfig"
1094 source "arch/arm/mach-shmobile/Kconfig"
1096 source "arch/arm/mach-sunxi/Kconfig"
1098 source "arch/arm/mach-prima2/Kconfig"
1100 source "arch/arm/mach-tegra/Kconfig"
1102 source "arch/arm/mach-u300/Kconfig"
1104 source "arch/arm/mach-ux500/Kconfig"
1106 source "arch/arm/mach-versatile/Kconfig"
1108 source "arch/arm/mach-vexpress/Kconfig"
1109 source "arch/arm/plat-versatile/Kconfig"
1111 source "arch/arm/mach-vt8500/Kconfig"
1113 source "arch/arm/mach-w90x900/Kconfig"
1115 source "arch/arm/mach-zynq/Kconfig"
1117 # Definitions to make life easier
1123 select GENERIC_CLOCKEVENTS
1129 select GENERIC_IRQ_CHIP
1132 config PLAT_ORION_LEGACY
1139 config PLAT_VERSATILE
1142 config ARM_TIMER_SP804
1145 select HAVE_SCHED_CLOCK
1147 source arch/arm/mm/Kconfig
1151 default 16 if ARCH_EP93XX
1155 bool "Enable iWMMXt support"
1156 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1157 default y if PXA27x || PXA3xx || ARCH_MMP
1159 Enable support for iWMMXt context switching at run time if
1160 running on a CPU that supports it.
1164 depends on CPU_XSCALE
1167 config MULTI_IRQ_HANDLER
1170 Allow each machine to specify it's own IRQ handler at run time.
1173 source "arch/arm/Kconfig-nommu"
1176 config ARM_ERRATA_326103
1177 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1180 Executing a SWP instruction to read-only memory does not set bit 11
1181 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1182 treat the access as a read, preventing a COW from occurring and
1183 causing the faulting task to livelock.
1185 config ARM_ERRATA_411920
1186 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1187 depends on CPU_V6 || CPU_V6K
1189 Invalidation of the Instruction Cache operation can
1190 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1191 It does not affect the MPCore. This option enables the ARM Ltd.
1192 recommended workaround.
1194 config ARM_ERRATA_430973
1195 bool "ARM errata: Stale prediction on replaced interworking branch"
1198 This option enables the workaround for the 430973 Cortex-A8
1199 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1200 interworking branch is replaced with another code sequence at the
1201 same virtual address, whether due to self-modifying code or virtual
1202 to physical address re-mapping, Cortex-A8 does not recover from the
1203 stale interworking branch prediction. This results in Cortex-A8
1204 executing the new code sequence in the incorrect ARM or Thumb state.
1205 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1206 and also flushes the branch target cache at every context switch.
1207 Note that setting specific bits in the ACTLR register may not be
1208 available in non-secure mode.
1210 config ARM_ERRATA_458693
1211 bool "ARM errata: Processor deadlock when a false hazard is created"
1213 depends on !ARCH_MULTIPLATFORM
1215 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1216 erratum. For very specific sequences of memory operations, it is
1217 possible for a hazard condition intended for a cache line to instead
1218 be incorrectly associated with a different cache line. This false
1219 hazard might then cause a processor deadlock. The workaround enables
1220 the L1 caching of the NEON accesses and disables the PLD instruction
1221 in the ACTLR register. Note that setting specific bits in the ACTLR
1222 register may not be available in non-secure mode.
1224 config ARM_ERRATA_460075
1225 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1227 depends on !ARCH_MULTIPLATFORM
1229 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1230 erratum. Any asynchronous access to the L2 cache may encounter a
1231 situation in which recent store transactions to the L2 cache are lost
1232 and overwritten with stale memory contents from external memory. The
1233 workaround disables the write-allocate mode for the L2 cache via the
1234 ACTLR register. Note that setting specific bits in the ACTLR register
1235 may not be available in non-secure mode.
1237 config ARM_ERRATA_742230
1238 bool "ARM errata: DMB operation may be faulty"
1239 depends on CPU_V7 && SMP
1240 depends on !ARCH_MULTIPLATFORM
1242 This option enables the workaround for the 742230 Cortex-A9
1243 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1244 between two write operations may not ensure the correct visibility
1245 ordering of the two writes. This workaround sets a specific bit in
1246 the diagnostic register of the Cortex-A9 which causes the DMB
1247 instruction to behave as a DSB, ensuring the correct behaviour of
1250 config ARM_ERRATA_742231
1251 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1252 depends on CPU_V7 && SMP
1253 depends on !ARCH_MULTIPLATFORM
1255 This option enables the workaround for the 742231 Cortex-A9
1256 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1257 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1258 accessing some data located in the same cache line, may get corrupted
1259 data due to bad handling of the address hazard when the line gets
1260 replaced from one of the CPUs at the same time as another CPU is
1261 accessing it. This workaround sets specific bits in the diagnostic
1262 register of the Cortex-A9 which reduces the linefill issuing
1263 capabilities of the processor.
1265 config PL310_ERRATA_588369
1266 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1267 depends on CACHE_L2X0
1269 The PL310 L2 cache controller implements three types of Clean &
1270 Invalidate maintenance operations: by Physical Address
1271 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1272 They are architecturally defined to behave as the execution of a
1273 clean operation followed immediately by an invalidate operation,
1274 both performing to the same memory location. This functionality
1275 is not correctly implemented in PL310 as clean lines are not
1276 invalidated as a result of these operations.
1278 config ARM_ERRATA_720789
1279 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1282 This option enables the workaround for the 720789 Cortex-A9 (prior to
1283 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1284 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1285 As a consequence of this erratum, some TLB entries which should be
1286 invalidated are not, resulting in an incoherency in the system page
1287 tables. The workaround changes the TLB flushing routines to invalidate
1288 entries regardless of the ASID.
1290 config PL310_ERRATA_727915
1291 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1292 depends on CACHE_L2X0
1294 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1295 operation (offset 0x7FC). This operation runs in background so that
1296 PL310 can handle normal accesses while it is in progress. Under very
1297 rare circumstances, due to this erratum, write data can be lost when
1298 PL310 treats a cacheable write transaction during a Clean &
1299 Invalidate by Way operation.
1301 config ARM_ERRATA_743622
1302 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1304 depends on !ARCH_MULTIPLATFORM
1306 This option enables the workaround for the 743622 Cortex-A9
1307 (r2p*) erratum. Under very rare conditions, a faulty
1308 optimisation in the Cortex-A9 Store Buffer may lead to data
1309 corruption. This workaround sets a specific bit in the diagnostic
1310 register of the Cortex-A9 which disables the Store Buffer
1311 optimisation, preventing the defect from occurring. This has no
1312 visible impact on the overall performance or power consumption of the
1315 config ARM_ERRATA_751472
1316 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1318 depends on !ARCH_MULTIPLATFORM
1320 This option enables the workaround for the 751472 Cortex-A9 (prior
1321 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1322 completion of a following broadcasted operation if the second
1323 operation is received by a CPU before the ICIALLUIS has completed,
1324 potentially leading to corrupted entries in the cache or TLB.
1326 config PL310_ERRATA_753970
1327 bool "PL310 errata: cache sync operation may be faulty"
1328 depends on CACHE_PL310
1330 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1332 Under some condition the effect of cache sync operation on
1333 the store buffer still remains when the operation completes.
1334 This means that the store buffer is always asked to drain and
1335 this prevents it from merging any further writes. The workaround
1336 is to replace the normal offset of cache sync operation (0x730)
1337 by another offset targeting an unmapped PL310 register 0x740.
1338 This has the same effect as the cache sync operation: store buffer
1339 drain and waiting for all buffers empty.
1341 config ARM_ERRATA_754322
1342 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1345 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1346 r3p*) erratum. A speculative memory access may cause a page table walk
1347 which starts prior to an ASID switch but completes afterwards. This
1348 can populate the micro-TLB with a stale entry which may be hit with
1349 the new ASID. This workaround places two dsb instructions in the mm
1350 switching code so that no page table walks can cross the ASID switch.
1352 config ARM_ERRATA_754327
1353 bool "ARM errata: no automatic Store Buffer drain"
1354 depends on CPU_V7 && SMP
1356 This option enables the workaround for the 754327 Cortex-A9 (prior to
1357 r2p0) erratum. The Store Buffer does not have any automatic draining
1358 mechanism and therefore a livelock may occur if an external agent
1359 continuously polls a memory location waiting to observe an update.
1360 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1361 written polling loops from denying visibility of updates to memory.
1363 config ARM_ERRATA_364296
1364 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1365 depends on CPU_V6 && !SMP
1367 This options enables the workaround for the 364296 ARM1136
1368 r0p2 erratum (possible cache data corruption with
1369 hit-under-miss enabled). It sets the undocumented bit 31 in
1370 the auxiliary control register and the FI bit in the control
1371 register, thus disabling hit-under-miss without putting the
1372 processor into full low interrupt latency mode. ARM11MPCore
1375 config ARM_ERRATA_764369
1376 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1377 depends on CPU_V7 && SMP
1379 This option enables the workaround for erratum 764369
1380 affecting Cortex-A9 MPCore with two or more processors (all
1381 current revisions). Under certain timing circumstances, a data
1382 cache line maintenance operation by MVA targeting an Inner
1383 Shareable memory region may fail to proceed up to either the
1384 Point of Coherency or to the Point of Unification of the
1385 system. This workaround adds a DSB instruction before the
1386 relevant cache maintenance functions and sets a specific bit
1387 in the diagnostic control register of the SCU.
1389 config PL310_ERRATA_769419
1390 bool "PL310 errata: no automatic Store Buffer drain"
1391 depends on CACHE_L2X0
1393 On revisions of the PL310 prior to r3p2, the Store Buffer does
1394 not automatically drain. This can cause normal, non-cacheable
1395 writes to be retained when the memory system is idle, leading
1396 to suboptimal I/O performance for drivers using coherent DMA.
1397 This option adds a write barrier to the cpu_idle loop so that,
1398 on systems with an outer cache, the store buffer is drained
1401 config ARM_ERRATA_775420
1402 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1405 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1406 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1407 operation aborts with MMU exception, it might cause the processor
1408 to deadlock. This workaround puts DSB before executing ISB if
1409 an abort may occur on cache maintenance.
1413 source "arch/arm/common/Kconfig"
1423 Find out whether you have ISA slots on your motherboard. ISA is the
1424 name of a bus system, i.e. the way the CPU talks to the other stuff
1425 inside your box. Other bus systems are PCI, EISA, MicroChannel
1426 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1427 newer boards don't support it. If you have ISA, say Y, otherwise N.
1429 # Select ISA DMA controller support
1434 config ARCH_NO_VIRT_TO_BUS
1436 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1438 # Select ISA DMA interface
1443 bool "PCI support" if MIGHT_HAVE_PCI
1445 Find out whether you have a PCI motherboard. PCI is the name of a
1446 bus system, i.e. the way the CPU talks to the other stuff inside
1447 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1448 VESA. If you have PCI, say Y, otherwise N.
1454 config PCI_NANOENGINE
1455 bool "BSE nanoEngine PCI support"
1456 depends on SA1100_NANOENGINE
1458 Enable PCI on the BSE nanoEngine board.
1463 # Select the host bridge type
1464 config PCI_HOST_VIA82C505
1466 depends on PCI && ARCH_SHARK
1469 config PCI_HOST_ITE8152
1471 depends on PCI && MACH_ARMCORE
1475 source "drivers/pci/Kconfig"
1477 source "drivers/pcmcia/Kconfig"
1481 menu "Kernel Features"
1486 This option should be selected by machines which have an SMP-
1489 The only effect of this option is to make the SMP-related
1490 options available to the user for configuration.
1493 bool "Symmetric Multi-Processing"
1494 depends on CPU_V6K || CPU_V7
1495 depends on GENERIC_CLOCKEVENTS
1498 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1499 select USE_GENERIC_SMP_HELPERS
1501 This enables support for systems with more than one CPU. If you have
1502 a system with only one CPU, like most personal computers, say N. If
1503 you have a system with more than one CPU, say Y.
1505 If you say N here, the kernel will run on single and multiprocessor
1506 machines, but will use only one CPU of a multiprocessor machine. If
1507 you say Y here, the kernel will run on many, but not all, single
1508 processor machines. On a single processor machine, the kernel will
1509 run faster if you say N here.
1511 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1512 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1513 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1515 If you don't know what to do here, say N.
1518 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1519 depends on SMP && !XIP_KERNEL
1522 SMP kernels contain instructions which fail on non-SMP processors.
1523 Enabling this option allows the kernel to modify itself to make
1524 these instructions safe. Disabling it allows about 1K of space
1527 If you don't know what to do here, say Y.
1529 config ARM_CPU_TOPOLOGY
1530 bool "Support cpu topology definition"
1531 depends on SMP && CPU_V7
1534 Support ARM cpu topology definition. The MPIDR register defines
1535 affinity between processors which is then used to describe the cpu
1536 topology of an ARM System.
1539 bool "Multi-core scheduler support"
1540 depends on ARM_CPU_TOPOLOGY
1542 Multi-core scheduler support improves the CPU scheduler's decision
1543 making when dealing with multi-core CPU chips at a cost of slightly
1544 increased overhead in some places. If unsure say N here.
1547 bool "SMT scheduler support"
1548 depends on ARM_CPU_TOPOLOGY
1550 Improves the CPU scheduler's decision making when dealing with
1551 MultiThreading at a cost of slightly increased overhead in some
1552 places. If unsure say N here.
1557 This option enables support for the ARM system coherency unit
1559 config ARM_ARCH_TIMER
1560 bool "Architected timer support"
1563 This option enables support for the ARM architected timer
1569 This options enables support for the ARM timer and watchdog unit
1572 prompt "Memory split"
1575 Select the desired split between kernel and user memory.
1577 If you are not absolutely sure what you are doing, leave this
1581 bool "3G/1G user/kernel split"
1583 bool "2G/2G user/kernel split"
1585 bool "1G/3G user/kernel split"
1590 default 0x40000000 if VMSPLIT_1G
1591 default 0x80000000 if VMSPLIT_2G
1595 int "Maximum number of CPUs (2-32)"
1601 bool "Support for hot-pluggable CPUs"
1602 depends on SMP && HOTPLUG
1604 Say Y here to experiment with turning CPUs off and on. CPUs
1605 can be controlled through /sys/devices/system/cpu.
1608 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1611 Say Y here if you want Linux to communicate with system firmware
1612 implementing the PSCI specification for CPU-centric power
1613 management operations described in ARM document number ARM DEN
1614 0022A ("Power State Coordination Interface System Software on
1618 bool "Use local timer interrupts"
1621 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1623 Enable support for local timers on SMP platforms, rather then the
1624 legacy IPI broadcast method. Local timers allows the system
1625 accounting to be spread across the timer interval, preventing a
1626 "thundering herd" at every timer tick.
1630 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1631 default 355 if ARCH_U8500
1632 default 264 if MACH_H4700
1633 default 512 if SOC_OMAP5
1634 default 288 if ARCH_VT8500 || ARCH_SUNXI
1637 Maximum number of GPIOs in the system.
1639 If unsure, leave the default value.
1641 source kernel/Kconfig.preempt
1645 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1646 ARCH_S5PV210 || ARCH_EXYNOS4
1647 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1648 default AT91_TIMER_HZ if ARCH_AT91
1649 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1653 def_bool HIGH_RES_TIMERS
1655 config THUMB2_KERNEL
1656 bool "Compile the kernel in Thumb-2 mode"
1657 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1659 select ARM_ASM_UNIFIED
1662 By enabling this option, the kernel will be compiled in
1663 Thumb-2 mode. A compiler/assembler that understand the unified
1664 ARM-Thumb syntax is needed.
1668 config THUMB2_AVOID_R_ARM_THM_JUMP11
1669 bool "Work around buggy Thumb-2 short branch relocations in gas"
1670 depends on THUMB2_KERNEL && MODULES
1673 Various binutils versions can resolve Thumb-2 branches to
1674 locally-defined, preemptible global symbols as short-range "b.n"
1675 branch instructions.
1677 This is a problem, because there's no guarantee the final
1678 destination of the symbol, or any candidate locations for a
1679 trampoline, are within range of the branch. For this reason, the
1680 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1681 relocation in modules at all, and it makes little sense to add
1684 The symptom is that the kernel fails with an "unsupported
1685 relocation" error when loading some modules.
1687 Until fixed tools are available, passing
1688 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1689 code which hits this problem, at the cost of a bit of extra runtime
1690 stack usage in some cases.
1692 The problem is described in more detail at:
1693 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1695 Only Thumb-2 kernels are affected.
1697 Unless you are sure your tools don't have this problem, say Y.
1699 config ARM_ASM_UNIFIED
1703 bool "Use the ARM EABI to compile the kernel"
1705 This option allows for the kernel to be compiled using the latest
1706 ARM ABI (aka EABI). This is only useful if you are using a user
1707 space environment that is also compiled with EABI.
1709 Since there are major incompatibilities between the legacy ABI and
1710 EABI, especially with regard to structure member alignment, this
1711 option also changes the kernel syscall calling convention to
1712 disambiguate both ABIs and allow for backward compatibility support
1713 (selected with CONFIG_OABI_COMPAT).
1715 To use this you need GCC version 4.0.0 or later.
1718 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1719 depends on AEABI && !THUMB2_KERNEL
1722 This option preserves the old syscall interface along with the
1723 new (ARM EABI) one. It also provides a compatibility layer to
1724 intercept syscalls that have structure arguments which layout
1725 in memory differs between the legacy ABI and the new ARM EABI
1726 (only for non "thumb" binaries). This option adds a tiny
1727 overhead to all syscalls and produces a slightly larger kernel.
1728 If you know you'll be using only pure EABI user space then you
1729 can say N here. If this option is not selected and you attempt
1730 to execute a legacy ABI binary then the result will be
1731 UNPREDICTABLE (in fact it can be predicted that it won't work
1732 at all). If in doubt say Y.
1734 config ARCH_HAS_HOLES_MEMORYMODEL
1737 config ARCH_SPARSEMEM_ENABLE
1740 config ARCH_SPARSEMEM_DEFAULT
1741 def_bool ARCH_SPARSEMEM_ENABLE
1743 config ARCH_SELECT_MEMORY_MODEL
1744 def_bool ARCH_SPARSEMEM_ENABLE
1746 config HAVE_ARCH_PFN_VALID
1747 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1750 bool "High Memory Support"
1753 The address space of ARM processors is only 4 Gigabytes large
1754 and it has to accommodate user address space, kernel address
1755 space as well as some memory mapped IO. That means that, if you
1756 have a large amount of physical memory and/or IO, not all of the
1757 memory can be "permanently mapped" by the kernel. The physical
1758 memory that is not permanently mapped is called "high memory".
1760 Depending on the selected kernel/user memory split, minimum
1761 vmalloc space and actual amount of RAM, you may not need this
1762 option which should result in a slightly faster kernel.
1767 bool "Allocate 2nd-level pagetables from highmem"
1770 config HW_PERF_EVENTS
1771 bool "Enable hardware performance counter support for perf events"
1772 depends on PERF_EVENTS
1775 Enable hardware performance counter support for perf events. If
1776 disabled, perf events will use software events only.
1780 config FORCE_MAX_ZONEORDER
1781 int "Maximum zone order" if ARCH_SHMOBILE
1782 range 11 64 if ARCH_SHMOBILE
1783 default "12" if SOC_AM33XX
1784 default "9" if SA1111
1787 The kernel memory allocator divides physically contiguous memory
1788 blocks into "zones", where each zone is a power of two number of
1789 pages. This option selects the largest power of two that the kernel
1790 keeps in the memory allocator. If you need to allocate very large
1791 blocks of physically contiguous memory, then you may need to
1792 increase this value.
1794 This config option is actually maximum order plus one. For example,
1795 a value of 11 means that the largest free memory block is 2^10 pages.
1797 config ALIGNMENT_TRAP
1799 depends on CPU_CP15_MMU
1800 default y if !ARCH_EBSA110
1801 select HAVE_PROC_CPU if PROC_FS
1803 ARM processors cannot fetch/store information which is not
1804 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1805 address divisible by 4. On 32-bit ARM processors, these non-aligned
1806 fetch/store instructions will be emulated in software if you say
1807 here, which has a severe performance impact. This is necessary for
1808 correct operation of some network protocols. With an IP-only
1809 configuration it is safe to say N, otherwise say Y.
1811 config UACCESS_WITH_MEMCPY
1812 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1814 default y if CPU_FEROCEON
1816 Implement faster copy_to_user and clear_user methods for CPU
1817 cores where a 8-word STM instruction give significantly higher
1818 memory write throughput than a sequence of individual 32bit stores.
1820 A possible side effect is a slight increase in scheduling latency
1821 between threads sharing the same address space if they invoke
1822 such copy operations with large buffers.
1824 However, if the CPU data cache is using a write-allocate mode,
1825 this option is unlikely to provide any performance gain.
1829 prompt "Enable seccomp to safely compute untrusted bytecode"
1831 This kernel feature is useful for number crunching applications
1832 that may need to compute untrusted bytecode during their
1833 execution. By using pipes or other transports made available to
1834 the process as file descriptors supporting the read/write
1835 syscalls, it's possible to isolate those applications in
1836 their own address space using seccomp. Once seccomp is
1837 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1838 and the task is only allowed to execute a few safe syscalls
1839 defined by each seccomp mode.
1841 config CC_STACKPROTECTOR
1842 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1844 This option turns on the -fstack-protector GCC feature. This
1845 feature puts, at the beginning of functions, a canary value on
1846 the stack just before the return address, and validates
1847 the value just before actually returning. Stack based buffer
1848 overflows (that need to overwrite this return address) now also
1849 overwrite the canary, which gets detected and the attack is then
1850 neutralized via a kernel panic.
1851 This feature requires gcc version 4.2 or above.
1858 bool "Xen guest support on ARM (EXPERIMENTAL)"
1859 depends on ARM && OF
1860 depends on CPU_V7 && !CPU_V6
1862 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1869 bool "Flattened Device Tree support"
1872 select OF_EARLY_FLATTREE
1874 Include support for flattened device tree machine descriptions.
1877 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1880 This is the traditional way of passing data to the kernel at boot
1881 time. If you are solely relying on the flattened device tree (or
1882 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1883 to remove ATAGS support from your kernel binary. If unsure,
1886 config DEPRECATED_PARAM_STRUCT
1887 bool "Provide old way to pass kernel parameters"
1890 This was deprecated in 2001 and announced to live on for 5 years.
1891 Some old boot loaders still use this way.
1893 # Compressed boot loader in ROM. Yes, we really want to ask about
1894 # TEXT and BSS so we preserve their values in the config files.
1895 config ZBOOT_ROM_TEXT
1896 hex "Compressed ROM boot loader base address"
1899 The physical address at which the ROM-able zImage is to be
1900 placed in the target. Platforms which normally make use of
1901 ROM-able zImage formats normally set this to a suitable
1902 value in their defconfig file.
1904 If ZBOOT_ROM is not enabled, this has no effect.
1906 config ZBOOT_ROM_BSS
1907 hex "Compressed ROM boot loader BSS address"
1910 The base address of an area of read/write memory in the target
1911 for the ROM-able zImage which must be available while the
1912 decompressor is running. It must be large enough to hold the
1913 entire decompressed kernel plus an additional 128 KiB.
1914 Platforms which normally make use of ROM-able zImage formats
1915 normally set this to a suitable value in their defconfig file.
1917 If ZBOOT_ROM is not enabled, this has no effect.
1920 bool "Compressed boot loader in ROM/flash"
1921 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1923 Say Y here if you intend to execute your compressed kernel image
1924 (zImage) directly from ROM or flash. If unsure, say N.
1927 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1928 depends on ZBOOT_ROM && ARCH_SH7372
1929 default ZBOOT_ROM_NONE
1931 Include experimental SD/MMC loading code in the ROM-able zImage.
1932 With this enabled it is possible to write the ROM-able zImage
1933 kernel image to an MMC or SD card and boot the kernel straight
1934 from the reset vector. At reset the processor Mask ROM will load
1935 the first part of the ROM-able zImage which in turn loads the
1936 rest the kernel image to RAM.
1938 config ZBOOT_ROM_NONE
1939 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1941 Do not load image from SD or MMC
1943 config ZBOOT_ROM_MMCIF
1944 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1946 Load image from MMCIF hardware block.
1948 config ZBOOT_ROM_SH_MOBILE_SDHI
1949 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1951 Load image from SDHI hardware block
1955 config ARM_APPENDED_DTB
1956 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1957 depends on OF && !ZBOOT_ROM
1959 With this option, the boot code will look for a device tree binary
1960 (DTB) appended to zImage
1961 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1963 This is meant as a backward compatibility convenience for those
1964 systems with a bootloader that can't be upgraded to accommodate
1965 the documented boot protocol using a device tree.
1967 Beware that there is very little in terms of protection against
1968 this option being confused by leftover garbage in memory that might
1969 look like a DTB header after a reboot if no actual DTB is appended
1970 to zImage. Do not leave this option active in a production kernel
1971 if you don't intend to always append a DTB. Proper passing of the
1972 location into r2 of a bootloader provided DTB is always preferable
1975 config ARM_ATAG_DTB_COMPAT
1976 bool "Supplement the appended DTB with traditional ATAG information"
1977 depends on ARM_APPENDED_DTB
1979 Some old bootloaders can't be updated to a DTB capable one, yet
1980 they provide ATAGs with memory configuration, the ramdisk address,
1981 the kernel cmdline string, etc. Such information is dynamically
1982 provided by the bootloader and can't always be stored in a static
1983 DTB. To allow a device tree enabled kernel to be used with such
1984 bootloaders, this option allows zImage to extract the information
1985 from the ATAG list and store it at run time into the appended DTB.
1988 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1989 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1991 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1992 bool "Use bootloader kernel arguments if available"
1994 Uses the command-line options passed by the boot loader instead of
1995 the device tree bootargs property. If the boot loader doesn't provide
1996 any, the device tree bootargs property will be used.
1998 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1999 bool "Extend with bootloader kernel arguments"
2001 The command-line arguments provided by the boot loader will be
2002 appended to the the device tree bootargs property.
2007 string "Default kernel command string"
2010 On some architectures (EBSA110 and CATS), there is currently no way
2011 for the boot loader to pass arguments to the kernel. For these
2012 architectures, you should supply some command-line options at build
2013 time by entering them here. As a minimum, you should specify the
2014 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2017 prompt "Kernel command line type" if CMDLINE != ""
2018 default CMDLINE_FROM_BOOTLOADER
2021 config CMDLINE_FROM_BOOTLOADER
2022 bool "Use bootloader kernel arguments if available"
2024 Uses the command-line options passed by the boot loader. If
2025 the boot loader doesn't provide any, the default kernel command
2026 string provided in CMDLINE will be used.
2028 config CMDLINE_EXTEND
2029 bool "Extend bootloader kernel arguments"
2031 The command-line arguments provided by the boot loader will be
2032 appended to the default kernel command string.
2034 config CMDLINE_FORCE
2035 bool "Always use the default kernel command string"
2037 Always use the default kernel command string, even if the boot
2038 loader passes other arguments to the kernel.
2039 This is useful if you cannot or don't want to change the
2040 command-line options your boot loader passes to the kernel.
2044 bool "Kernel Execute-In-Place from ROM"
2045 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2047 Execute-In-Place allows the kernel to run from non-volatile storage
2048 directly addressable by the CPU, such as NOR flash. This saves RAM
2049 space since the text section of the kernel is not loaded from flash
2050 to RAM. Read-write sections, such as the data section and stack,
2051 are still copied to RAM. The XIP kernel is not compressed since
2052 it has to run directly from flash, so it will take more space to
2053 store it. The flash address used to link the kernel object files,
2054 and for storing it, is configuration dependent. Therefore, if you
2055 say Y here, you must know the proper physical address where to
2056 store the kernel image depending on your own flash memory usage.
2058 Also note that the make target becomes "make xipImage" rather than
2059 "make zImage" or "make Image". The final kernel binary to put in
2060 ROM memory will be arch/arm/boot/xipImage.
2064 config XIP_PHYS_ADDR
2065 hex "XIP Kernel Physical Location"
2066 depends on XIP_KERNEL
2067 default "0x00080000"
2069 This is the physical address in your flash memory the kernel will
2070 be linked for and stored to. This address is dependent on your
2074 bool "Kexec system call (EXPERIMENTAL)"
2075 depends on (!SMP || HOTPLUG_CPU)
2077 kexec is a system call that implements the ability to shutdown your
2078 current kernel, and to start another kernel. It is like a reboot
2079 but it is independent of the system firmware. And like a reboot
2080 you can start any kernel with it, not just Linux.
2082 It is an ongoing process to be certain the hardware in a machine
2083 is properly shutdown, so do not be surprised if this code does not
2084 initially work for you. It may help to enable device hotplugging
2088 bool "Export atags in procfs"
2089 depends on ATAGS && KEXEC
2092 Should the atags used to boot the kernel be exported in an "atags"
2093 file in procfs. Useful with kexec.
2096 bool "Build kdump crash kernel (EXPERIMENTAL)"
2098 Generate crash dump after being started by kexec. This should
2099 be normally only set in special crash dump kernels which are
2100 loaded in the main kernel with kexec-tools into a specially
2101 reserved region and then later executed after a crash by
2102 kdump/kexec. The crash dump kernel must be compiled to a
2103 memory address not used by the main kernel
2105 For more details see Documentation/kdump/kdump.txt
2107 config AUTO_ZRELADDR
2108 bool "Auto calculation of the decompressed kernel image address"
2109 depends on !ZBOOT_ROM && !ARCH_U300
2111 ZRELADDR is the physical address where the decompressed kernel
2112 image will be placed. If AUTO_ZRELADDR is selected, the address
2113 will be determined at run-time by masking the current IP with
2114 0xf8000000. This assumes the zImage being placed in the first 128MB
2115 from start of memory.
2119 menu "CPU Power Management"
2123 source "drivers/cpufreq/Kconfig"
2126 tristate "CPUfreq driver for i.MX CPUs"
2127 depends on ARCH_MXC && CPU_FREQ
2128 select CPU_FREQ_TABLE
2130 This enables the CPUfreq driver for i.MX CPUs.
2132 config CPU_FREQ_SA1100
2135 config CPU_FREQ_SA1110
2138 config CPU_FREQ_INTEGRATOR
2139 tristate "CPUfreq driver for ARM Integrator CPUs"
2140 depends on ARCH_INTEGRATOR && CPU_FREQ
2143 This enables the CPUfreq driver for ARM Integrator CPUs.
2145 For details, take a look at <file:Documentation/cpu-freq>.
2151 depends on CPU_FREQ && ARCH_PXA && PXA25x
2153 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2154 select CPU_FREQ_TABLE
2159 Internal configuration node for common cpufreq on Samsung SoC
2161 config CPU_FREQ_S3C24XX
2162 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2163 depends on ARCH_S3C24XX && CPU_FREQ
2166 This enables the CPUfreq driver for the Samsung S3C24XX family
2169 For details, take a look at <file:Documentation/cpu-freq>.
2173 config CPU_FREQ_S3C24XX_PLL
2174 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2175 depends on CPU_FREQ_S3C24XX
2177 Compile in support for changing the PLL frequency from the
2178 S3C24XX series CPUfreq driver. The PLL takes time to settle
2179 after a frequency change, so by default it is not enabled.
2181 This also means that the PLL tables for the selected CPU(s) will
2182 be built which may increase the size of the kernel image.
2184 config CPU_FREQ_S3C24XX_DEBUG
2185 bool "Debug CPUfreq Samsung driver core"
2186 depends on CPU_FREQ_S3C24XX
2188 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2190 config CPU_FREQ_S3C24XX_IODEBUG
2191 bool "Debug CPUfreq Samsung driver IO timing"
2192 depends on CPU_FREQ_S3C24XX
2194 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2196 config CPU_FREQ_S3C24XX_DEBUGFS
2197 bool "Export debugfs for CPUFreq"
2198 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2200 Export status information via debugfs.
2204 source "drivers/cpuidle/Kconfig"
2208 menu "Floating point emulation"
2210 comment "At least one emulation must be selected"
2213 bool "NWFPE math emulation"
2214 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2216 Say Y to include the NWFPE floating point emulator in the kernel.
2217 This is necessary to run most binaries. Linux does not currently
2218 support floating point hardware so you need to say Y here even if
2219 your machine has an FPA or floating point co-processor podule.
2221 You may say N here if you are going to load the Acorn FPEmulator
2222 early in the bootup.
2225 bool "Support extended precision"
2226 depends on FPE_NWFPE
2228 Say Y to include 80-bit support in the kernel floating-point
2229 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2230 Note that gcc does not generate 80-bit operations by default,
2231 so in most cases this option only enlarges the size of the
2232 floating point emulator without any good reason.
2234 You almost surely want to say N here.
2237 bool "FastFPE math emulation (EXPERIMENTAL)"
2238 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2240 Say Y here to include the FAST floating point emulator in the kernel.
2241 This is an experimental much faster emulator which now also has full
2242 precision for the mantissa. It does not support any exceptions.
2243 It is very simple, and approximately 3-6 times faster than NWFPE.
2245 It should be sufficient for most programs. It may be not suitable
2246 for scientific calculations, but you have to check this for yourself.
2247 If you do not feel you need a faster FP emulation you should better
2251 bool "VFP-format floating point maths"
2252 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2254 Say Y to include VFP support code in the kernel. This is needed
2255 if your hardware includes a VFP unit.
2257 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2258 release notes and additional status information.
2260 Say N if your target does not have VFP hardware.
2268 bool "Advanced SIMD (NEON) Extension support"
2269 depends on VFPv3 && CPU_V7
2271 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2276 menu "Userspace binary formats"
2278 source "fs/Kconfig.binfmt"
2281 tristate "RISC OS personality"
2284 Say Y here to include the kernel code necessary if you want to run
2285 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2286 experimental; if this sounds frightening, say N and sleep in peace.
2287 You can also say M here to compile this support as a module (which
2288 will be called arthur).
2292 menu "Power management options"
2294 source "kernel/power/Kconfig"
2296 config ARCH_SUSPEND_POSSIBLE
2297 depends on !ARCH_S5PC100
2298 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2299 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2302 config ARM_CPU_SUSPEND
2307 source "net/Kconfig"
2309 source "drivers/Kconfig"
2313 source "arch/arm/Kconfig.debug"
2315 source "security/Kconfig"
2317 source "crypto/Kconfig"
2319 source "lib/Kconfig"
2321 source "arch/arm/kvm/Kconfig"