4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
82 config ARM_DMA_IOMMU_ALIGNMENT
83 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 DMA mapping framework by default aligns all buffers to the smallest
88 PAGE_SIZE order which is greater than or equal to the requested buffer
89 size. This works well for buffers up to a few hundreds kilobytes, but
90 for larger buffers it just a waste of address space. Drivers which has
91 relatively small addressing window (like 64Mib) might run out of
92 virtual space with just a few allocations.
94 With this parameter you can specify the maximum PAGE_SIZE order for
95 DMA IOMMU buffers. Larger buffers will be aligned only to this
96 specified order. The order is expressed as a power of two multiplied
104 config MIGHT_HAVE_PCI
107 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Broadcom BCM2835 family"
366 select ARCH_REQUIRE_GPIOLIB
368 select ARM_ERRATA_411920
369 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select MULTI_IRQ_HANDLER
377 select PINCTRL_BCM2835
381 This enables support for the Broadcom BCM2835 SoC. This SoC is
382 use in the Raspberry Pi, and Roku 2 devices.
385 bool "Cavium Networks CNS3XXX family"
388 select GENERIC_CLOCKEVENTS
389 select MIGHT_HAVE_CACHE_L2X0
390 select MIGHT_HAVE_PCI
391 select PCI_DOMAINS if PCI
393 Support for Cavium Networks CNS3XXX platform.
396 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
397 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
403 select MULTI_IRQ_HANDLER
404 select NEED_MACH_MEMORY_H
407 Support for Cirrus Logic 711x/721x/731x based boards.
410 bool "Cortina Systems Gemini"
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
415 Support for the Cortina Systems Gemini family SoCs
419 select ARCH_REQUIRE_GPIOLIB
422 select GENERIC_CLOCKEVENTS
423 select GENERIC_IRQ_CHIP
424 select MIGHT_HAVE_CACHE_L2X0
430 Support for CSR SiRFprimaII/Marco/Polo platforms
434 select ARCH_USES_GETTIMEOFFSET
437 select NEED_MACH_IO_H
438 select NEED_MACH_MEMORY_H
441 This is an evaluation board for the StrongARM processor available
442 from Digital. It has limited hardware on-board, including an
443 Ethernet interface, two PCMCIA sockets, two serial ports and a
448 select ARCH_HAS_HOLES_MEMORYMODEL
449 select ARCH_REQUIRE_GPIOLIB
450 select ARCH_USES_GETTIMEOFFSET
455 select NEED_MACH_MEMORY_H
457 This enables support for the Cirrus EP93xx series of CPUs.
459 config ARCH_FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS
465 select NEED_MACH_IO_H if !MMU
466 select NEED_MACH_MEMORY_H
468 Support for systems based on the DC21285 companion chip
469 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
472 bool "Freescale MXS-based"
473 select ARCH_REQUIRE_GPIOLIB
477 select GENERIC_CLOCKEVENTS
478 select HAVE_CLK_PREPARE
479 select MULTI_IRQ_HANDLER
484 Support for Freescale MXS-based family of processors
487 bool "Hilscher NetX based"
491 select GENERIC_CLOCKEVENTS
493 This enables support for systems based on the Hilscher NetX Soc
496 bool "Hynix HMS720x-based"
497 select ARCH_USES_GETTIMEOFFSET
501 This enables support for systems based on the Hynix HMS720x
506 select ARCH_SUPPORTS_MSI
508 select NEED_MACH_MEMORY_H
509 select NEED_RET_TO_USER
514 Support for Intel's IOP13XX (XScale) family of processors.
519 select ARCH_REQUIRE_GPIOLIB
521 select NEED_MACH_GPIO_H
522 select NEED_RET_TO_USER
526 Support for Intel's 80219 and IOP32X (XScale) family of
532 select ARCH_REQUIRE_GPIOLIB
534 select NEED_MACH_GPIO_H
535 select NEED_RET_TO_USER
539 Support for Intel's IOP33X (XScale) family of processors.
544 select ARCH_HAS_DMA_SET_COHERENT_MASK
545 select ARCH_REQUIRE_GPIOLIB
548 select DMABOUNCE if PCI
549 select GENERIC_CLOCKEVENTS
550 select MIGHT_HAVE_PCI
551 select NEED_MACH_IO_H
553 Support for Intel's IXP4XX (XScale) family of processors.
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
560 select MIGHT_HAVE_PCI
563 select PLAT_ORION_LEGACY
564 select USB_ARCH_HAS_EHCI
566 Support for the Marvell Dove SoC 88AP510
569 bool "Marvell Kirkwood"
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
576 select PINCTRL_KIRKWOOD
577 select PLAT_ORION_LEGACY
579 Support for the following Marvell Kirkwood series SoCs:
580 88F6180, 88F6192 and 88F6281.
583 bool "Marvell MV78xx0"
584 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_CLOCKEVENTS
588 select PLAT_ORION_LEGACY
590 Support for the following Marvell MV78xx0 series SoCs:
596 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
600 select PLAT_ORION_LEGACY
602 Support for the following Marvell Orion 5x series SoCs:
603 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
604 Orion-2 (5281), Orion-1-90 (6183).
607 bool "Marvell PXA168/910/MMP2"
609 select ARCH_REQUIRE_GPIOLIB
611 select GENERIC_ALLOCATOR
612 select GENERIC_CLOCKEVENTS
615 select NEED_MACH_GPIO_H
620 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
623 bool "Micrel/Kendin KS8695"
624 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
628 select NEED_MACH_MEMORY_H
630 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
631 System-on-Chip devices.
634 bool "Nuvoton W90X900 CPU"
635 select ARCH_REQUIRE_GPIOLIB
639 select GENERIC_CLOCKEVENTS
641 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
642 At present, the w90x900 has been renamed nuc900, regarding
643 the ARM series product line, you can login the following
644 link address to know more.
646 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
647 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
651 select ARCH_REQUIRE_GPIOLIB
656 select GENERIC_CLOCKEVENTS
659 select USB_ARCH_HAS_OHCI
662 Support for the NXP LPC32XX family of processors
666 select ARCH_HAS_CPUFREQ
667 select ARCH_REQUIRE_GPIOLIB
672 select GENERIC_CLOCKEVENTS
675 select MIGHT_HAVE_CACHE_L2X0
679 This enables support for NVIDIA Tegra based systems (Tegra APX,
680 Tegra 6xx and Tegra 2 series).
683 bool "PXA2xx/PXA3xx-based"
685 select ARCH_HAS_CPUFREQ
687 select ARCH_REQUIRE_GPIOLIB
688 select ARM_CPU_SUSPEND if PM
692 select GENERIC_CLOCKEVENTS
695 select MULTI_IRQ_HANDLER
696 select NEED_MACH_GPIO_H
700 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
704 select ARCH_REQUIRE_GPIOLIB
706 select GENERIC_CLOCKEVENTS
709 Support for Qualcomm MSM/QSD based systems. This runs on the
710 apps processor of the MSM/QSD and depends on a shared memory
711 interface to the modem processor which runs the baseband
712 stack and controls some vital subsystems
713 (clock and power control, etc).
716 bool "Renesas SH-Mobile / R-Mobile"
718 select GENERIC_CLOCKEVENTS
720 select HAVE_MACH_CLKDEV
722 select MIGHT_HAVE_CACHE_L2X0
723 select MULTI_IRQ_HANDLER
724 select NEED_MACH_MEMORY_H
727 select PM_GENERIC_DOMAINS if PM
730 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
735 select ARCH_MAY_HAVE_PC_FDC
736 select ARCH_SPARSEMEM_ENABLE
737 select ARCH_USES_GETTIMEOFFSET
740 select HAVE_PATA_PLATFORM
742 select NEED_MACH_IO_H
743 select NEED_MACH_MEMORY_H
747 On the Acorn Risc-PC, Linux can support the internal IDE disk and
748 CD-ROM interface, serial and parallel port, and the floppy drive.
752 select ARCH_HAS_CPUFREQ
754 select ARCH_REQUIRE_GPIOLIB
755 select ARCH_SPARSEMEM_ENABLE
760 select GENERIC_CLOCKEVENTS
763 select NEED_MACH_GPIO_H
764 select NEED_MACH_MEMORY_H
767 Support for StrongARM 11x0 based boards.
770 bool "Samsung S3C24XX SoCs"
771 select ARCH_HAS_CPUFREQ
774 select GENERIC_CLOCKEVENTS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
781 select NEED_MACH_IO_H
783 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
784 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
785 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
786 Samsung SMDK2410 development board (and derivatives).
789 bool "Samsung S3C64XX"
790 select ARCH_HAS_CPUFREQ
791 select ARCH_REQUIRE_GPIOLIB
796 select GENERIC_CLOCKEVENTS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select NEED_MACH_GPIO_H
805 select S3C_GPIO_TRACK
806 select SAMSUNG_CLKSRC
807 select SAMSUNG_GPIOLIB_4BIT
808 select SAMSUNG_IRQ_VIC_TIMER
809 select USB_ARCH_HAS_OHCI
811 Samsung S3C64XX series based systems
814 bool "Samsung S5P6440 S5P6450"
818 select GENERIC_CLOCKEVENTS
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select HAVE_S3C_RTC if RTC_CLASS
823 select NEED_MACH_GPIO_H
825 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
829 bool "Samsung S5PC100"
833 select GENERIC_CLOCKEVENTS
836 select HAVE_S3C2410_I2C if I2C
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
838 select HAVE_S3C_RTC if RTC_CLASS
839 select NEED_MACH_GPIO_H
841 Samsung S5PC100 series based systems
844 bool "Samsung S5PV210/S5PC110"
845 select ARCH_HAS_CPUFREQ
846 select ARCH_HAS_HOLES_MEMORYMODEL
847 select ARCH_SPARSEMEM_ENABLE
851 select GENERIC_CLOCKEVENTS
853 select HAVE_S3C2410_I2C if I2C
854 select HAVE_S3C2410_WATCHDOG if WATCHDOG
855 select HAVE_S3C_RTC if RTC_CLASS
856 select NEED_MACH_GPIO_H
857 select NEED_MACH_MEMORY_H
859 Samsung S5PV210/S5PC110 series based systems
862 bool "Samsung EXYNOS"
863 select ARCH_HAS_CPUFREQ
864 select ARCH_HAS_HOLES_MEMORYMODEL
865 select ARCH_SPARSEMEM_ENABLE
869 select GENERIC_CLOCKEVENTS
871 select HAVE_S3C2410_I2C if I2C
872 select HAVE_S3C2410_WATCHDOG if WATCHDOG
873 select HAVE_S3C_RTC if RTC_CLASS
874 select NEED_MACH_GPIO_H
875 select NEED_MACH_MEMORY_H
877 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
881 select ARCH_USES_GETTIMEOFFSET
885 select NEED_MACH_MEMORY_H
890 Support for the StrongARM based Digital DNARD machine, also known
891 as "Shark" (<http://www.shark-linux.de/shark.html>).
894 bool "ST-Ericsson U300 Series"
896 select ARCH_REQUIRE_GPIOLIB
898 select ARM_PATCH_PHYS_VIRT
904 select GENERIC_CLOCKEVENTS
908 Support for ST-Ericsson U300 series mobile platforms.
911 bool "ST-Ericsson U8500 Series"
913 select ARCH_HAS_CPUFREQ
914 select ARCH_REQUIRE_GPIOLIB
918 select GENERIC_CLOCKEVENTS
920 select MIGHT_HAVE_CACHE_L2X0
923 Support for ST-Ericsson's Ux500 architecture
926 bool "STMicroelectronics Nomadik"
927 select ARCH_REQUIRE_GPIOLIB
930 select CLKSRC_NOMADIK_MTU
933 select GENERIC_CLOCKEVENTS
934 select MIGHT_HAVE_CACHE_L2X0
937 select PINCTRL_STN8815
940 Support for the Nomadik platform by ST-Ericsson
944 select ARCH_HAS_CPUFREQ
945 select ARCH_REQUIRE_GPIOLIB
950 select GENERIC_CLOCKEVENTS
953 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
957 select ARCH_HAS_HOLES_MEMORYMODEL
958 select ARCH_REQUIRE_GPIOLIB
960 select GENERIC_ALLOCATOR
961 select GENERIC_CLOCKEVENTS
962 select GENERIC_IRQ_CHIP
964 select NEED_MACH_GPIO_H
968 Support for TI's DaVinci platform.
973 select ARCH_HAS_CPUFREQ
974 select ARCH_HAS_HOLES_MEMORYMODEL
976 select ARCH_REQUIRE_GPIOLIB
979 select GENERIC_CLOCKEVENTS
980 select GENERIC_IRQ_CHIP
984 select NEED_MACH_IO_H if PCCARD
985 select NEED_MACH_MEMORY_H
987 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
991 menu "Multiple platform selection"
992 depends on ARCH_MULTIPLATFORM
994 comment "CPU Core family selection"
997 bool "ARMv4 based platforms (FA526, StrongARM)"
998 depends on !ARCH_MULTI_V6_V7
999 select ARCH_MULTI_V4_V5
1001 config ARCH_MULTI_V4T
1002 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
1003 depends on !ARCH_MULTI_V6_V7
1004 select ARCH_MULTI_V4_V5
1006 config ARCH_MULTI_V5
1007 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1008 depends on !ARCH_MULTI_V6_V7
1009 select ARCH_MULTI_V4_V5
1011 config ARCH_MULTI_V4_V5
1014 config ARCH_MULTI_V6
1015 bool "ARMv6 based platforms (ARM11)"
1016 select ARCH_MULTI_V6_V7
1019 config ARCH_MULTI_V7
1020 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1022 select ARCH_MULTI_V6_V7
1023 select ARCH_VEXPRESS
1026 config ARCH_MULTI_V6_V7
1029 config ARCH_MULTI_CPU_AUTO
1030 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1031 select ARCH_MULTI_V5
1036 # This is sorted alphabetically by mach-* pathname. However, plat-*
1037 # Kconfigs may be included either alphabetically (according to the
1038 # plat- suffix) or along side the corresponding mach-* source.
1040 source "arch/arm/mach-mvebu/Kconfig"
1042 source "arch/arm/mach-at91/Kconfig"
1044 source "arch/arm/mach-bcm/Kconfig"
1046 source "arch/arm/mach-clps711x/Kconfig"
1048 source "arch/arm/mach-cns3xxx/Kconfig"
1050 source "arch/arm/mach-davinci/Kconfig"
1052 source "arch/arm/mach-dove/Kconfig"
1054 source "arch/arm/mach-ep93xx/Kconfig"
1056 source "arch/arm/mach-footbridge/Kconfig"
1058 source "arch/arm/mach-gemini/Kconfig"
1060 source "arch/arm/mach-h720x/Kconfig"
1062 source "arch/arm/mach-highbank/Kconfig"
1064 source "arch/arm/mach-integrator/Kconfig"
1066 source "arch/arm/mach-iop32x/Kconfig"
1068 source "arch/arm/mach-iop33x/Kconfig"
1070 source "arch/arm/mach-iop13xx/Kconfig"
1072 source "arch/arm/mach-ixp4xx/Kconfig"
1074 source "arch/arm/mach-kirkwood/Kconfig"
1076 source "arch/arm/mach-ks8695/Kconfig"
1078 source "arch/arm/mach-msm/Kconfig"
1080 source "arch/arm/mach-mv78xx0/Kconfig"
1082 source "arch/arm/mach-imx/Kconfig"
1084 source "arch/arm/mach-mxs/Kconfig"
1086 source "arch/arm/mach-netx/Kconfig"
1088 source "arch/arm/mach-nomadik/Kconfig"
1090 source "arch/arm/plat-omap/Kconfig"
1092 source "arch/arm/mach-omap1/Kconfig"
1094 source "arch/arm/mach-omap2/Kconfig"
1096 source "arch/arm/mach-orion5x/Kconfig"
1098 source "arch/arm/mach-picoxcell/Kconfig"
1100 source "arch/arm/mach-pxa/Kconfig"
1101 source "arch/arm/plat-pxa/Kconfig"
1103 source "arch/arm/mach-mmp/Kconfig"
1105 source "arch/arm/mach-realview/Kconfig"
1107 source "arch/arm/mach-sa1100/Kconfig"
1109 source "arch/arm/plat-samsung/Kconfig"
1111 source "arch/arm/mach-socfpga/Kconfig"
1113 source "arch/arm/plat-spear/Kconfig"
1115 source "arch/arm/mach-s3c24xx/Kconfig"
1118 source "arch/arm/mach-s3c64xx/Kconfig"
1121 source "arch/arm/mach-s5p64x0/Kconfig"
1123 source "arch/arm/mach-s5pc100/Kconfig"
1125 source "arch/arm/mach-s5pv210/Kconfig"
1127 source "arch/arm/mach-exynos/Kconfig"
1129 source "arch/arm/mach-shmobile/Kconfig"
1131 source "arch/arm/mach-sunxi/Kconfig"
1133 source "arch/arm/mach-prima2/Kconfig"
1135 source "arch/arm/mach-tegra/Kconfig"
1137 source "arch/arm/mach-u300/Kconfig"
1139 source "arch/arm/mach-ux500/Kconfig"
1141 source "arch/arm/mach-versatile/Kconfig"
1143 source "arch/arm/mach-vexpress/Kconfig"
1144 source "arch/arm/plat-versatile/Kconfig"
1146 source "arch/arm/mach-virt/Kconfig"
1148 source "arch/arm/mach-vt8500/Kconfig"
1150 source "arch/arm/mach-w90x900/Kconfig"
1152 source "arch/arm/mach-zynq/Kconfig"
1154 # Definitions to make life easier
1160 select GENERIC_CLOCKEVENTS
1166 select GENERIC_IRQ_CHIP
1169 config PLAT_ORION_LEGACY
1176 config PLAT_VERSATILE
1179 config ARM_TIMER_SP804
1182 select HAVE_SCHED_CLOCK
1184 source arch/arm/mm/Kconfig
1188 default 16 if ARCH_EP93XX
1192 bool "Enable iWMMXt support" if !CPU_PJ4
1193 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1194 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1196 Enable support for iWMMXt context switching at run time if
1197 running on a CPU that supports it.
1201 depends on CPU_XSCALE
1204 config MULTI_IRQ_HANDLER
1207 Allow each machine to specify it's own IRQ handler at run time.
1210 source "arch/arm/Kconfig-nommu"
1213 config ARM_ERRATA_326103
1214 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1217 Executing a SWP instruction to read-only memory does not set bit 11
1218 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1219 treat the access as a read, preventing a COW from occurring and
1220 causing the faulting task to livelock.
1222 config ARM_ERRATA_411920
1223 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1224 depends on CPU_V6 || CPU_V6K
1226 Invalidation of the Instruction Cache operation can
1227 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1228 It does not affect the MPCore. This option enables the ARM Ltd.
1229 recommended workaround.
1231 config ARM_ERRATA_430973
1232 bool "ARM errata: Stale prediction on replaced interworking branch"
1235 This option enables the workaround for the 430973 Cortex-A8
1236 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1237 interworking branch is replaced with another code sequence at the
1238 same virtual address, whether due to self-modifying code or virtual
1239 to physical address re-mapping, Cortex-A8 does not recover from the
1240 stale interworking branch prediction. This results in Cortex-A8
1241 executing the new code sequence in the incorrect ARM or Thumb state.
1242 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1243 and also flushes the branch target cache at every context switch.
1244 Note that setting specific bits in the ACTLR register may not be
1245 available in non-secure mode.
1247 config ARM_ERRATA_458693
1248 bool "ARM errata: Processor deadlock when a false hazard is created"
1250 depends on !ARCH_MULTIPLATFORM
1252 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1253 erratum. For very specific sequences of memory operations, it is
1254 possible for a hazard condition intended for a cache line to instead
1255 be incorrectly associated with a different cache line. This false
1256 hazard might then cause a processor deadlock. The workaround enables
1257 the L1 caching of the NEON accesses and disables the PLD instruction
1258 in the ACTLR register. Note that setting specific bits in the ACTLR
1259 register may not be available in non-secure mode.
1261 config ARM_ERRATA_460075
1262 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1264 depends on !ARCH_MULTIPLATFORM
1266 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1267 erratum. Any asynchronous access to the L2 cache may encounter a
1268 situation in which recent store transactions to the L2 cache are lost
1269 and overwritten with stale memory contents from external memory. The
1270 workaround disables the write-allocate mode for the L2 cache via the
1271 ACTLR register. Note that setting specific bits in the ACTLR register
1272 may not be available in non-secure mode.
1274 config ARM_ERRATA_742230
1275 bool "ARM errata: DMB operation may be faulty"
1276 depends on CPU_V7 && SMP
1277 depends on !ARCH_MULTIPLATFORM
1279 This option enables the workaround for the 742230 Cortex-A9
1280 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1281 between two write operations may not ensure the correct visibility
1282 ordering of the two writes. This workaround sets a specific bit in
1283 the diagnostic register of the Cortex-A9 which causes the DMB
1284 instruction to behave as a DSB, ensuring the correct behaviour of
1287 config ARM_ERRATA_742231
1288 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1289 depends on CPU_V7 && SMP
1290 depends on !ARCH_MULTIPLATFORM
1292 This option enables the workaround for the 742231 Cortex-A9
1293 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1294 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1295 accessing some data located in the same cache line, may get corrupted
1296 data due to bad handling of the address hazard when the line gets
1297 replaced from one of the CPUs at the same time as another CPU is
1298 accessing it. This workaround sets specific bits in the diagnostic
1299 register of the Cortex-A9 which reduces the linefill issuing
1300 capabilities of the processor.
1302 config PL310_ERRATA_588369
1303 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1304 depends on CACHE_L2X0
1306 The PL310 L2 cache controller implements three types of Clean &
1307 Invalidate maintenance operations: by Physical Address
1308 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1309 They are architecturally defined to behave as the execution of a
1310 clean operation followed immediately by an invalidate operation,
1311 both performing to the same memory location. This functionality
1312 is not correctly implemented in PL310 as clean lines are not
1313 invalidated as a result of these operations.
1315 config ARM_ERRATA_720789
1316 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1319 This option enables the workaround for the 720789 Cortex-A9 (prior to
1320 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1321 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1322 As a consequence of this erratum, some TLB entries which should be
1323 invalidated are not, resulting in an incoherency in the system page
1324 tables. The workaround changes the TLB flushing routines to invalidate
1325 entries regardless of the ASID.
1327 config PL310_ERRATA_727915
1328 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1329 depends on CACHE_L2X0
1331 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1332 operation (offset 0x7FC). This operation runs in background so that
1333 PL310 can handle normal accesses while it is in progress. Under very
1334 rare circumstances, due to this erratum, write data can be lost when
1335 PL310 treats a cacheable write transaction during a Clean &
1336 Invalidate by Way operation.
1338 config ARM_ERRATA_743622
1339 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1341 depends on !ARCH_MULTIPLATFORM
1343 This option enables the workaround for the 743622 Cortex-A9
1344 (r2p*) erratum. Under very rare conditions, a faulty
1345 optimisation in the Cortex-A9 Store Buffer may lead to data
1346 corruption. This workaround sets a specific bit in the diagnostic
1347 register of the Cortex-A9 which disables the Store Buffer
1348 optimisation, preventing the defect from occurring. This has no
1349 visible impact on the overall performance or power consumption of the
1352 config ARM_ERRATA_751472
1353 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1355 depends on !ARCH_MULTIPLATFORM
1357 This option enables the workaround for the 751472 Cortex-A9 (prior
1358 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1359 completion of a following broadcasted operation if the second
1360 operation is received by a CPU before the ICIALLUIS has completed,
1361 potentially leading to corrupted entries in the cache or TLB.
1363 config PL310_ERRATA_753970
1364 bool "PL310 errata: cache sync operation may be faulty"
1365 depends on CACHE_PL310
1367 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1369 Under some condition the effect of cache sync operation on
1370 the store buffer still remains when the operation completes.
1371 This means that the store buffer is always asked to drain and
1372 this prevents it from merging any further writes. The workaround
1373 is to replace the normal offset of cache sync operation (0x730)
1374 by another offset targeting an unmapped PL310 register 0x740.
1375 This has the same effect as the cache sync operation: store buffer
1376 drain and waiting for all buffers empty.
1378 config ARM_ERRATA_754322
1379 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1382 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1383 r3p*) erratum. A speculative memory access may cause a page table walk
1384 which starts prior to an ASID switch but completes afterwards. This
1385 can populate the micro-TLB with a stale entry which may be hit with
1386 the new ASID. This workaround places two dsb instructions in the mm
1387 switching code so that no page table walks can cross the ASID switch.
1389 config ARM_ERRATA_754327
1390 bool "ARM errata: no automatic Store Buffer drain"
1391 depends on CPU_V7 && SMP
1393 This option enables the workaround for the 754327 Cortex-A9 (prior to
1394 r2p0) erratum. The Store Buffer does not have any automatic draining
1395 mechanism and therefore a livelock may occur if an external agent
1396 continuously polls a memory location waiting to observe an update.
1397 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1398 written polling loops from denying visibility of updates to memory.
1400 config ARM_ERRATA_364296
1401 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1402 depends on CPU_V6 && !SMP
1404 This options enables the workaround for the 364296 ARM1136
1405 r0p2 erratum (possible cache data corruption with
1406 hit-under-miss enabled). It sets the undocumented bit 31 in
1407 the auxiliary control register and the FI bit in the control
1408 register, thus disabling hit-under-miss without putting the
1409 processor into full low interrupt latency mode. ARM11MPCore
1412 config ARM_ERRATA_764369
1413 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1414 depends on CPU_V7 && SMP
1416 This option enables the workaround for erratum 764369
1417 affecting Cortex-A9 MPCore with two or more processors (all
1418 current revisions). Under certain timing circumstances, a data
1419 cache line maintenance operation by MVA targeting an Inner
1420 Shareable memory region may fail to proceed up to either the
1421 Point of Coherency or to the Point of Unification of the
1422 system. This workaround adds a DSB instruction before the
1423 relevant cache maintenance functions and sets a specific bit
1424 in the diagnostic control register of the SCU.
1426 config PL310_ERRATA_769419
1427 bool "PL310 errata: no automatic Store Buffer drain"
1428 depends on CACHE_L2X0
1430 On revisions of the PL310 prior to r3p2, the Store Buffer does
1431 not automatically drain. This can cause normal, non-cacheable
1432 writes to be retained when the memory system is idle, leading
1433 to suboptimal I/O performance for drivers using coherent DMA.
1434 This option adds a write barrier to the cpu_idle loop so that,
1435 on systems with an outer cache, the store buffer is drained
1438 config ARM_ERRATA_775420
1439 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1442 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1443 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1444 operation aborts with MMU exception, it might cause the processor
1445 to deadlock. This workaround puts DSB before executing ISB if
1446 an abort may occur on cache maintenance.
1448 config ARM_ERRATA_798181
1449 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1450 depends on CPU_V7 && SMP
1452 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1453 adequately shooting down all use of the old entries. This
1454 option enables the Linux kernel workaround for this erratum
1455 which sends an IPI to the CPUs that are running the same ASID
1456 as the one being invalidated.
1460 source "arch/arm/common/Kconfig"
1470 Find out whether you have ISA slots on your motherboard. ISA is the
1471 name of a bus system, i.e. the way the CPU talks to the other stuff
1472 inside your box. Other bus systems are PCI, EISA, MicroChannel
1473 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1474 newer boards don't support it. If you have ISA, say Y, otherwise N.
1476 # Select ISA DMA controller support
1481 # Select ISA DMA interface
1486 bool "PCI support" if MIGHT_HAVE_PCI
1488 Find out whether you have a PCI motherboard. PCI is the name of a
1489 bus system, i.e. the way the CPU talks to the other stuff inside
1490 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1491 VESA. If you have PCI, say Y, otherwise N.
1497 config PCI_NANOENGINE
1498 bool "BSE nanoEngine PCI support"
1499 depends on SA1100_NANOENGINE
1501 Enable PCI on the BSE nanoEngine board.
1506 # Select the host bridge type
1507 config PCI_HOST_VIA82C505
1509 depends on PCI && ARCH_SHARK
1512 config PCI_HOST_ITE8152
1514 depends on PCI && MACH_ARMCORE
1518 source "drivers/pci/Kconfig"
1520 source "drivers/pcmcia/Kconfig"
1524 menu "Kernel Features"
1529 This option should be selected by machines which have an SMP-
1532 The only effect of this option is to make the SMP-related
1533 options available to the user for configuration.
1536 bool "Symmetric Multi-Processing"
1537 depends on CPU_V6K || CPU_V7
1538 depends on GENERIC_CLOCKEVENTS
1541 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1542 select USE_GENERIC_SMP_HELPERS
1544 This enables support for systems with more than one CPU. If you have
1545 a system with only one CPU, like most personal computers, say N. If
1546 you have a system with more than one CPU, say Y.
1548 If you say N here, the kernel will run on single and multiprocessor
1549 machines, but will use only one CPU of a multiprocessor machine. If
1550 you say Y here, the kernel will run on many, but not all, single
1551 processor machines. On a single processor machine, the kernel will
1552 run faster if you say N here.
1554 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1555 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1556 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1558 If you don't know what to do here, say N.
1561 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1562 depends on SMP && !XIP_KERNEL
1565 SMP kernels contain instructions which fail on non-SMP processors.
1566 Enabling this option allows the kernel to modify itself to make
1567 these instructions safe. Disabling it allows about 1K of space
1570 If you don't know what to do here, say Y.
1572 config ARM_CPU_TOPOLOGY
1573 bool "Support cpu topology definition"
1574 depends on SMP && CPU_V7
1577 Support ARM cpu topology definition. The MPIDR register defines
1578 affinity between processors which is then used to describe the cpu
1579 topology of an ARM System.
1582 bool "Multi-core scheduler support"
1583 depends on ARM_CPU_TOPOLOGY
1585 Multi-core scheduler support improves the CPU scheduler's decision
1586 making when dealing with multi-core CPU chips at a cost of slightly
1587 increased overhead in some places. If unsure say N here.
1590 bool "SMT scheduler support"
1591 depends on ARM_CPU_TOPOLOGY
1593 Improves the CPU scheduler's decision making when dealing with
1594 MultiThreading at a cost of slightly increased overhead in some
1595 places. If unsure say N here.
1600 This option enables support for the ARM system coherency unit
1602 config HAVE_ARM_ARCH_TIMER
1603 bool "Architected timer support"
1605 select ARM_ARCH_TIMER
1607 This option enables support for the ARM architected timer
1613 This options enables support for the ARM timer and watchdog unit
1616 prompt "Memory split"
1619 Select the desired split between kernel and user memory.
1621 If you are not absolutely sure what you are doing, leave this
1625 bool "3G/1G user/kernel split"
1627 bool "2G/2G user/kernel split"
1629 bool "1G/3G user/kernel split"
1634 default 0x40000000 if VMSPLIT_1G
1635 default 0x80000000 if VMSPLIT_2G
1639 int "Maximum number of CPUs (2-32)"
1645 bool "Support for hot-pluggable CPUs"
1646 depends on SMP && HOTPLUG
1648 Say Y here to experiment with turning CPUs off and on. CPUs
1649 can be controlled through /sys/devices/system/cpu.
1652 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1655 Say Y here if you want Linux to communicate with system firmware
1656 implementing the PSCI specification for CPU-centric power
1657 management operations described in ARM document number ARM DEN
1658 0022A ("Power State Coordination Interface System Software on
1662 bool "Use local timer interrupts"
1665 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
1667 Enable support for local timers on SMP platforms, rather then the
1668 legacy IPI broadcast method. Local timers allows the system
1669 accounting to be spread across the timer interval, preventing a
1670 "thundering herd" at every timer tick.
1672 # The GPIO number here must be sorted by descending number. In case of
1673 # a multiplatform kernel, we just want the highest value required by the
1674 # selected platforms.
1677 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1678 default 512 if SOC_OMAP5
1679 default 355 if ARCH_U8500
1680 default 288 if ARCH_VT8500 || ARCH_SUNXI
1681 default 264 if MACH_H4700
1684 Maximum number of GPIOs in the system.
1686 If unsure, leave the default value.
1688 source kernel/Kconfig.preempt
1692 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1693 ARCH_S5PV210 || ARCH_EXYNOS4
1694 default AT91_TIMER_HZ if ARCH_AT91
1695 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1699 def_bool HIGH_RES_TIMERS
1701 config THUMB2_KERNEL
1702 bool "Compile the kernel in Thumb-2 mode"
1703 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1705 select ARM_ASM_UNIFIED
1708 By enabling this option, the kernel will be compiled in
1709 Thumb-2 mode. A compiler/assembler that understand the unified
1710 ARM-Thumb syntax is needed.
1714 config THUMB2_AVOID_R_ARM_THM_JUMP11
1715 bool "Work around buggy Thumb-2 short branch relocations in gas"
1716 depends on THUMB2_KERNEL && MODULES
1719 Various binutils versions can resolve Thumb-2 branches to
1720 locally-defined, preemptible global symbols as short-range "b.n"
1721 branch instructions.
1723 This is a problem, because there's no guarantee the final
1724 destination of the symbol, or any candidate locations for a
1725 trampoline, are within range of the branch. For this reason, the
1726 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1727 relocation in modules at all, and it makes little sense to add
1730 The symptom is that the kernel fails with an "unsupported
1731 relocation" error when loading some modules.
1733 Until fixed tools are available, passing
1734 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1735 code which hits this problem, at the cost of a bit of extra runtime
1736 stack usage in some cases.
1738 The problem is described in more detail at:
1739 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1741 Only Thumb-2 kernels are affected.
1743 Unless you are sure your tools don't have this problem, say Y.
1745 config ARM_ASM_UNIFIED
1749 bool "Use the ARM EABI to compile the kernel"
1751 This option allows for the kernel to be compiled using the latest
1752 ARM ABI (aka EABI). This is only useful if you are using a user
1753 space environment that is also compiled with EABI.
1755 Since there are major incompatibilities between the legacy ABI and
1756 EABI, especially with regard to structure member alignment, this
1757 option also changes the kernel syscall calling convention to
1758 disambiguate both ABIs and allow for backward compatibility support
1759 (selected with CONFIG_OABI_COMPAT).
1761 To use this you need GCC version 4.0.0 or later.
1764 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1765 depends on AEABI && !THUMB2_KERNEL
1768 This option preserves the old syscall interface along with the
1769 new (ARM EABI) one. It also provides a compatibility layer to
1770 intercept syscalls that have structure arguments which layout
1771 in memory differs between the legacy ABI and the new ARM EABI
1772 (only for non "thumb" binaries). This option adds a tiny
1773 overhead to all syscalls and produces a slightly larger kernel.
1774 If you know you'll be using only pure EABI user space then you
1775 can say N here. If this option is not selected and you attempt
1776 to execute a legacy ABI binary then the result will be
1777 UNPREDICTABLE (in fact it can be predicted that it won't work
1778 at all). If in doubt say Y.
1780 config ARCH_HAS_HOLES_MEMORYMODEL
1783 config ARCH_SPARSEMEM_ENABLE
1786 config ARCH_SPARSEMEM_DEFAULT
1787 def_bool ARCH_SPARSEMEM_ENABLE
1789 config ARCH_SELECT_MEMORY_MODEL
1790 def_bool ARCH_SPARSEMEM_ENABLE
1792 config HAVE_ARCH_PFN_VALID
1793 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1796 bool "High Memory Support"
1799 The address space of ARM processors is only 4 Gigabytes large
1800 and it has to accommodate user address space, kernel address
1801 space as well as some memory mapped IO. That means that, if you
1802 have a large amount of physical memory and/or IO, not all of the
1803 memory can be "permanently mapped" by the kernel. The physical
1804 memory that is not permanently mapped is called "high memory".
1806 Depending on the selected kernel/user memory split, minimum
1807 vmalloc space and actual amount of RAM, you may not need this
1808 option which should result in a slightly faster kernel.
1813 bool "Allocate 2nd-level pagetables from highmem"
1816 config HW_PERF_EVENTS
1817 bool "Enable hardware performance counter support for perf events"
1818 depends on PERF_EVENTS
1821 Enable hardware performance counter support for perf events. If
1822 disabled, perf events will use software events only.
1826 config FORCE_MAX_ZONEORDER
1827 int "Maximum zone order" if ARCH_SHMOBILE
1828 range 11 64 if ARCH_SHMOBILE
1829 default "12" if SOC_AM33XX
1830 default "9" if SA1111
1833 The kernel memory allocator divides physically contiguous memory
1834 blocks into "zones", where each zone is a power of two number of
1835 pages. This option selects the largest power of two that the kernel
1836 keeps in the memory allocator. If you need to allocate very large
1837 blocks of physically contiguous memory, then you may need to
1838 increase this value.
1840 This config option is actually maximum order plus one. For example,
1841 a value of 11 means that the largest free memory block is 2^10 pages.
1843 config ALIGNMENT_TRAP
1845 depends on CPU_CP15_MMU
1846 default y if !ARCH_EBSA110
1847 select HAVE_PROC_CPU if PROC_FS
1849 ARM processors cannot fetch/store information which is not
1850 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1851 address divisible by 4. On 32-bit ARM processors, these non-aligned
1852 fetch/store instructions will be emulated in software if you say
1853 here, which has a severe performance impact. This is necessary for
1854 correct operation of some network protocols. With an IP-only
1855 configuration it is safe to say N, otherwise say Y.
1857 config UACCESS_WITH_MEMCPY
1858 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1860 default y if CPU_FEROCEON
1862 Implement faster copy_to_user and clear_user methods for CPU
1863 cores where a 8-word STM instruction give significantly higher
1864 memory write throughput than a sequence of individual 32bit stores.
1866 A possible side effect is a slight increase in scheduling latency
1867 between threads sharing the same address space if they invoke
1868 such copy operations with large buffers.
1870 However, if the CPU data cache is using a write-allocate mode,
1871 this option is unlikely to provide any performance gain.
1875 prompt "Enable seccomp to safely compute untrusted bytecode"
1877 This kernel feature is useful for number crunching applications
1878 that may need to compute untrusted bytecode during their
1879 execution. By using pipes or other transports made available to
1880 the process as file descriptors supporting the read/write
1881 syscalls, it's possible to isolate those applications in
1882 their own address space using seccomp. Once seccomp is
1883 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1884 and the task is only allowed to execute a few safe syscalls
1885 defined by each seccomp mode.
1887 config CC_STACKPROTECTOR
1888 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1890 This option turns on the -fstack-protector GCC feature. This
1891 feature puts, at the beginning of functions, a canary value on
1892 the stack just before the return address, and validates
1893 the value just before actually returning. Stack based buffer
1894 overflows (that need to overwrite this return address) now also
1895 overwrite the canary, which gets detected and the attack is then
1896 neutralized via a kernel panic.
1897 This feature requires gcc version 4.2 or above.
1904 bool "Xen guest support on ARM (EXPERIMENTAL)"
1905 depends on ARM && AEABI && OF
1906 depends on CPU_V7 && !CPU_V6
1907 depends on !GENERIC_ATOMIC64
1909 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1916 bool "Flattened Device Tree support"
1919 select OF_EARLY_FLATTREE
1921 Include support for flattened device tree machine descriptions.
1924 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1927 This is the traditional way of passing data to the kernel at boot
1928 time. If you are solely relying on the flattened device tree (or
1929 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1930 to remove ATAGS support from your kernel binary. If unsure,
1933 config DEPRECATED_PARAM_STRUCT
1934 bool "Provide old way to pass kernel parameters"
1937 This was deprecated in 2001 and announced to live on for 5 years.
1938 Some old boot loaders still use this way.
1940 # Compressed boot loader in ROM. Yes, we really want to ask about
1941 # TEXT and BSS so we preserve their values in the config files.
1942 config ZBOOT_ROM_TEXT
1943 hex "Compressed ROM boot loader base address"
1946 The physical address at which the ROM-able zImage is to be
1947 placed in the target. Platforms which normally make use of
1948 ROM-able zImage formats normally set this to a suitable
1949 value in their defconfig file.
1951 If ZBOOT_ROM is not enabled, this has no effect.
1953 config ZBOOT_ROM_BSS
1954 hex "Compressed ROM boot loader BSS address"
1957 The base address of an area of read/write memory in the target
1958 for the ROM-able zImage which must be available while the
1959 decompressor is running. It must be large enough to hold the
1960 entire decompressed kernel plus an additional 128 KiB.
1961 Platforms which normally make use of ROM-able zImage formats
1962 normally set this to a suitable value in their defconfig file.
1964 If ZBOOT_ROM is not enabled, this has no effect.
1967 bool "Compressed boot loader in ROM/flash"
1968 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1970 Say Y here if you intend to execute your compressed kernel image
1971 (zImage) directly from ROM or flash. If unsure, say N.
1974 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1975 depends on ZBOOT_ROM && ARCH_SH7372
1976 default ZBOOT_ROM_NONE
1978 Include experimental SD/MMC loading code in the ROM-able zImage.
1979 With this enabled it is possible to write the ROM-able zImage
1980 kernel image to an MMC or SD card and boot the kernel straight
1981 from the reset vector. At reset the processor Mask ROM will load
1982 the first part of the ROM-able zImage which in turn loads the
1983 rest the kernel image to RAM.
1985 config ZBOOT_ROM_NONE
1986 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1988 Do not load image from SD or MMC
1990 config ZBOOT_ROM_MMCIF
1991 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1993 Load image from MMCIF hardware block.
1995 config ZBOOT_ROM_SH_MOBILE_SDHI
1996 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1998 Load image from SDHI hardware block
2002 config ARM_APPENDED_DTB
2003 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2004 depends on OF && !ZBOOT_ROM
2006 With this option, the boot code will look for a device tree binary
2007 (DTB) appended to zImage
2008 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2010 This is meant as a backward compatibility convenience for those
2011 systems with a bootloader that can't be upgraded to accommodate
2012 the documented boot protocol using a device tree.
2014 Beware that there is very little in terms of protection against
2015 this option being confused by leftover garbage in memory that might
2016 look like a DTB header after a reboot if no actual DTB is appended
2017 to zImage. Do not leave this option active in a production kernel
2018 if you don't intend to always append a DTB. Proper passing of the
2019 location into r2 of a bootloader provided DTB is always preferable
2022 config ARM_ATAG_DTB_COMPAT
2023 bool "Supplement the appended DTB with traditional ATAG information"
2024 depends on ARM_APPENDED_DTB
2026 Some old bootloaders can't be updated to a DTB capable one, yet
2027 they provide ATAGs with memory configuration, the ramdisk address,
2028 the kernel cmdline string, etc. Such information is dynamically
2029 provided by the bootloader and can't always be stored in a static
2030 DTB. To allow a device tree enabled kernel to be used with such
2031 bootloaders, this option allows zImage to extract the information
2032 from the ATAG list and store it at run time into the appended DTB.
2035 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2036 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2038 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2039 bool "Use bootloader kernel arguments if available"
2041 Uses the command-line options passed by the boot loader instead of
2042 the device tree bootargs property. If the boot loader doesn't provide
2043 any, the device tree bootargs property will be used.
2045 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2046 bool "Extend with bootloader kernel arguments"
2048 The command-line arguments provided by the boot loader will be
2049 appended to the the device tree bootargs property.
2054 string "Default kernel command string"
2057 On some architectures (EBSA110 and CATS), there is currently no way
2058 for the boot loader to pass arguments to the kernel. For these
2059 architectures, you should supply some command-line options at build
2060 time by entering them here. As a minimum, you should specify the
2061 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2064 prompt "Kernel command line type" if CMDLINE != ""
2065 default CMDLINE_FROM_BOOTLOADER
2068 config CMDLINE_FROM_BOOTLOADER
2069 bool "Use bootloader kernel arguments if available"
2071 Uses the command-line options passed by the boot loader. If
2072 the boot loader doesn't provide any, the default kernel command
2073 string provided in CMDLINE will be used.
2075 config CMDLINE_EXTEND
2076 bool "Extend bootloader kernel arguments"
2078 The command-line arguments provided by the boot loader will be
2079 appended to the default kernel command string.
2081 config CMDLINE_FORCE
2082 bool "Always use the default kernel command string"
2084 Always use the default kernel command string, even if the boot
2085 loader passes other arguments to the kernel.
2086 This is useful if you cannot or don't want to change the
2087 command-line options your boot loader passes to the kernel.
2091 bool "Kernel Execute-In-Place from ROM"
2092 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2094 Execute-In-Place allows the kernel to run from non-volatile storage
2095 directly addressable by the CPU, such as NOR flash. This saves RAM
2096 space since the text section of the kernel is not loaded from flash
2097 to RAM. Read-write sections, such as the data section and stack,
2098 are still copied to RAM. The XIP kernel is not compressed since
2099 it has to run directly from flash, so it will take more space to
2100 store it. The flash address used to link the kernel object files,
2101 and for storing it, is configuration dependent. Therefore, if you
2102 say Y here, you must know the proper physical address where to
2103 store the kernel image depending on your own flash memory usage.
2105 Also note that the make target becomes "make xipImage" rather than
2106 "make zImage" or "make Image". The final kernel binary to put in
2107 ROM memory will be arch/arm/boot/xipImage.
2111 config XIP_PHYS_ADDR
2112 hex "XIP Kernel Physical Location"
2113 depends on XIP_KERNEL
2114 default "0x00080000"
2116 This is the physical address in your flash memory the kernel will
2117 be linked for and stored to. This address is dependent on your
2121 bool "Kexec system call (EXPERIMENTAL)"
2122 depends on (!SMP || HOTPLUG_CPU)
2124 kexec is a system call that implements the ability to shutdown your
2125 current kernel, and to start another kernel. It is like a reboot
2126 but it is independent of the system firmware. And like a reboot
2127 you can start any kernel with it, not just Linux.
2129 It is an ongoing process to be certain the hardware in a machine
2130 is properly shutdown, so do not be surprised if this code does not
2131 initially work for you. It may help to enable device hotplugging
2135 bool "Export atags in procfs"
2136 depends on ATAGS && KEXEC
2139 Should the atags used to boot the kernel be exported in an "atags"
2140 file in procfs. Useful with kexec.
2143 bool "Build kdump crash kernel (EXPERIMENTAL)"
2145 Generate crash dump after being started by kexec. This should
2146 be normally only set in special crash dump kernels which are
2147 loaded in the main kernel with kexec-tools into a specially
2148 reserved region and then later executed after a crash by
2149 kdump/kexec. The crash dump kernel must be compiled to a
2150 memory address not used by the main kernel
2152 For more details see Documentation/kdump/kdump.txt
2154 config AUTO_ZRELADDR
2155 bool "Auto calculation of the decompressed kernel image address"
2156 depends on !ZBOOT_ROM && !ARCH_U300
2158 ZRELADDR is the physical address where the decompressed kernel
2159 image will be placed. If AUTO_ZRELADDR is selected, the address
2160 will be determined at run-time by masking the current IP with
2161 0xf8000000. This assumes the zImage being placed in the first 128MB
2162 from start of memory.
2166 menu "CPU Power Management"
2170 source "drivers/cpufreq/Kconfig"
2173 tristate "CPUfreq driver for i.MX CPUs"
2174 depends on ARCH_MXC && CPU_FREQ
2175 select CPU_FREQ_TABLE
2177 This enables the CPUfreq driver for i.MX CPUs.
2179 config CPU_FREQ_SA1100
2182 config CPU_FREQ_SA1110
2185 config CPU_FREQ_INTEGRATOR
2186 tristate "CPUfreq driver for ARM Integrator CPUs"
2187 depends on ARCH_INTEGRATOR && CPU_FREQ
2190 This enables the CPUfreq driver for ARM Integrator CPUs.
2192 For details, take a look at <file:Documentation/cpu-freq>.
2198 depends on CPU_FREQ && ARCH_PXA && PXA25x
2200 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2201 select CPU_FREQ_TABLE
2206 Internal configuration node for common cpufreq on Samsung SoC
2208 config CPU_FREQ_S3C24XX
2209 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2210 depends on ARCH_S3C24XX && CPU_FREQ
2213 This enables the CPUfreq driver for the Samsung S3C24XX family
2216 For details, take a look at <file:Documentation/cpu-freq>.
2220 config CPU_FREQ_S3C24XX_PLL
2221 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2222 depends on CPU_FREQ_S3C24XX
2224 Compile in support for changing the PLL frequency from the
2225 S3C24XX series CPUfreq driver. The PLL takes time to settle
2226 after a frequency change, so by default it is not enabled.
2228 This also means that the PLL tables for the selected CPU(s) will
2229 be built which may increase the size of the kernel image.
2231 config CPU_FREQ_S3C24XX_DEBUG
2232 bool "Debug CPUfreq Samsung driver core"
2233 depends on CPU_FREQ_S3C24XX
2235 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2237 config CPU_FREQ_S3C24XX_IODEBUG
2238 bool "Debug CPUfreq Samsung driver IO timing"
2239 depends on CPU_FREQ_S3C24XX
2241 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2243 config CPU_FREQ_S3C24XX_DEBUGFS
2244 bool "Export debugfs for CPUFreq"
2245 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2247 Export status information via debugfs.
2251 source "drivers/cpuidle/Kconfig"
2255 menu "Floating point emulation"
2257 comment "At least one emulation must be selected"
2260 bool "NWFPE math emulation"
2261 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2263 Say Y to include the NWFPE floating point emulator in the kernel.
2264 This is necessary to run most binaries. Linux does not currently
2265 support floating point hardware so you need to say Y here even if
2266 your machine has an FPA or floating point co-processor podule.
2268 You may say N here if you are going to load the Acorn FPEmulator
2269 early in the bootup.
2272 bool "Support extended precision"
2273 depends on FPE_NWFPE
2275 Say Y to include 80-bit support in the kernel floating-point
2276 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2277 Note that gcc does not generate 80-bit operations by default,
2278 so in most cases this option only enlarges the size of the
2279 floating point emulator without any good reason.
2281 You almost surely want to say N here.
2284 bool "FastFPE math emulation (EXPERIMENTAL)"
2285 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2287 Say Y here to include the FAST floating point emulator in the kernel.
2288 This is an experimental much faster emulator which now also has full
2289 precision for the mantissa. It does not support any exceptions.
2290 It is very simple, and approximately 3-6 times faster than NWFPE.
2292 It should be sufficient for most programs. It may be not suitable
2293 for scientific calculations, but you have to check this for yourself.
2294 If you do not feel you need a faster FP emulation you should better
2298 bool "VFP-format floating point maths"
2299 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2301 Say Y to include VFP support code in the kernel. This is needed
2302 if your hardware includes a VFP unit.
2304 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2305 release notes and additional status information.
2307 Say N if your target does not have VFP hardware.
2315 bool "Advanced SIMD (NEON) Extension support"
2316 depends on VFPv3 && CPU_V7
2318 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2323 menu "Userspace binary formats"
2325 source "fs/Kconfig.binfmt"
2328 tristate "RISC OS personality"
2331 Say Y here to include the kernel code necessary if you want to run
2332 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2333 experimental; if this sounds frightening, say N and sleep in peace.
2334 You can also say M here to compile this support as a module (which
2335 will be called arthur).
2339 menu "Power management options"
2341 source "kernel/power/Kconfig"
2343 config ARCH_SUSPEND_POSSIBLE
2344 depends on !ARCH_S5PC100
2345 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2346 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2349 config ARM_CPU_SUSPEND
2354 source "net/Kconfig"
2356 source "drivers/Kconfig"
2360 source "arch/arm/Kconfig.debug"
2362 source "security/Kconfig"
2364 source "crypto/Kconfig"
2366 source "lib/Kconfig"
2368 source "arch/arm/kvm/Kconfig"