5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
72 select GENERIC_ALLOCATOR
83 The Extended Industry Standard Architecture (EISA) bus was
84 developed as an open alternative to the IBM MicroChannel bus.
86 The EISA bus provided some of the features of the IBM MicroChannel
87 bus while maintaining backward compatibility with cards made for
88 the older ISA bus. The EISA bus saw limited use between 1988 and
89 1995 when it was made obsolete by the PCI bus.
91 Say Y here if you are building a kernel for an EISA-based machine.
101 MicroChannel Architecture is found in some IBM PS/2 machines and
102 laptops. It is a bus system similar to PCI or ISA. See
103 <file:Documentation/mca.txt> (and especially the web page given
104 there) before attempting to build an MCA bus kernel.
106 config STACKTRACE_SUPPORT
110 config HAVE_LATENCYTOP_SUPPORT
115 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
123 config HARDIRQS_SW_RESEND
127 config GENERIC_IRQ_PROBE
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 The base address of exception vectors.
193 config ARM_PATCH_PHYS_VIRT
194 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
195 depends on EXPERIMENTAL
196 depends on !XIP_KERNEL && MMU
197 depends on !ARCH_REALVIEW || !SPARSEMEM
199 Patch phys-to-virt translation functions at runtime according to
200 the position of the kernel in system memory.
202 This can only be used with non-XIP with MMU kernels where
203 the base of physical memory is at a 16MB boundary.
205 config ARM_PATCH_PHYS_VIRT_16BIT
207 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
209 source "init/Kconfig"
211 source "kernel/Kconfig.freezer"
216 bool "MMU-based Paged Memory Management Support"
219 Select if you want MMU-based virtualised addressing space
220 support by paged memory management. If unsure, say 'Y'.
223 # The "ARM system type" choice list is ordered alphabetically by option
224 # text. Please add new entries in the option alphabetic order.
227 prompt "ARM system type"
228 default ARCH_VERSATILE
231 bool "Agilent AAEC-2000 based"
235 select ARCH_USES_GETTIMEOFFSET
237 This enables support for systems based on the Agilent AAEC-2000
239 config ARCH_INTEGRATOR
240 bool "ARM Ltd. Integrator family"
242 select ARCH_HAS_CPUFREQ
245 select GENERIC_CLOCKEVENTS
246 select PLAT_VERSATILE
248 Support for ARM's Integrator platform.
251 bool "ARM Ltd. RealView family"
254 select HAVE_SCHED_CLOCK
256 select GENERIC_CLOCKEVENTS
257 select ARCH_WANT_OPTIONAL_GPIOLIB
258 select PLAT_VERSATILE
259 select ARM_TIMER_SP804
260 select GPIO_PL061 if GPIOLIB
262 This enables support for ARM Ltd RealView boards.
264 config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
269 select HAVE_SCHED_CLOCK
271 select GENERIC_CLOCKEVENTS
272 select ARCH_WANT_OPTIONAL_GPIOLIB
273 select PLAT_VERSATILE
274 select ARM_TIMER_SP804
276 This enables support for ARM Ltd Versatile board.
279 bool "ARM Ltd. Versatile Express family"
280 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select ARM_TIMER_SP804
284 select GENERIC_CLOCKEVENTS
286 select HAVE_SCHED_CLOCK
288 select PLAT_VERSATILE
290 This enables support for the ARM Ltd Versatile Express boards.
294 select ARCH_REQUIRE_GPIOLIB
297 This enables support for systems based on the Atmel AT91RM9200,
298 AT91SAM9 and AT91CAP9 processors.
301 bool "Broadcom BCMRING"
306 select GENERIC_CLOCKEVENTS
307 select ARCH_WANT_OPTIONAL_GPIOLIB
309 Support for Broadcom's BCMRing platform.
312 bool "Cirrus Logic CLPS711x/EP721x-based"
314 select ARCH_USES_GETTIMEOFFSET
316 Support for Cirrus Logic 711x/721x based boards.
319 bool "Cavium Networks CNS3XXX family"
321 select GENERIC_CLOCKEVENTS
323 select MIGHT_HAVE_PCI
324 select PCI_DOMAINS if PCI
326 Support for Cavium Networks CNS3XXX platform.
329 bool "Cortina Systems Gemini"
331 select ARCH_REQUIRE_GPIOLIB
332 select ARCH_USES_GETTIMEOFFSET
334 Support for the Cortina Systems Gemini family SoCs
341 select ARCH_USES_GETTIMEOFFSET
343 This is an evaluation board for the StrongARM processor available
344 from Digital. It has limited hardware on-board, including an
345 Ethernet interface, two PCMCIA sockets, two serial ports and a
354 select ARCH_REQUIRE_GPIOLIB
355 select ARCH_HAS_HOLES_MEMORYMODEL
356 select ARCH_USES_GETTIMEOFFSET
358 This enables support for the Cirrus EP93xx series of CPUs.
360 config ARCH_FOOTBRIDGE
364 select GENERIC_CLOCKEVENTS
366 Support for systems based on the DC21285 companion chip
367 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
370 bool "Freescale MXC/iMX-based"
371 select GENERIC_CLOCKEVENTS
372 select ARCH_REQUIRE_GPIOLIB
375 Support for Freescale MXC/iMX-based family of processors
378 bool "Freescale MXS-based"
379 select GENERIC_CLOCKEVENTS
380 select ARCH_REQUIRE_GPIOLIB
383 Support for Freescale MXS-based family of processors
386 bool "Freescale STMP3xxx"
389 select ARCH_REQUIRE_GPIOLIB
390 select GENERIC_CLOCKEVENTS
391 select USB_ARCH_HAS_EHCI
393 Support for systems based on the Freescale 3xxx CPUs.
396 bool "Hilscher NetX based"
399 select GENERIC_CLOCKEVENTS
401 This enables support for systems based on the Hilscher NetX Soc
404 bool "Hynix HMS720x-based"
407 select ARCH_USES_GETTIMEOFFSET
409 This enables support for systems based on the Hynix HMS720x
417 select ARCH_SUPPORTS_MSI
420 Support for Intel's IOP13XX (XScale) family of processors.
428 select ARCH_REQUIRE_GPIOLIB
430 Support for Intel's 80219 and IOP32X (XScale) family of
439 select ARCH_REQUIRE_GPIOLIB
441 Support for Intel's IOP33X (XScale) family of processors.
448 select ARCH_USES_GETTIMEOFFSET
450 Support for Intel's IXP23xx (XScale) family of processors.
453 bool "IXP2400/2800-based"
457 select ARCH_USES_GETTIMEOFFSET
459 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
505 select ARCH_REQUIRE_GPIOLIB
508 select USB_ARCH_HAS_OHCI
511 select GENERIC_CLOCKEVENTS
513 Support for the NXP LPC32XX family of processors
516 bool "Marvell MV78xx0"
519 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
523 Support for the following Marvell MV78xx0 series SoCs:
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 Support for the following Marvell Orion 5x series SoCs:
536 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
537 Orion-2 (5281), Orion-1-90 (6183).
540 bool "Marvell PXA168/910/MMP2"
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
545 select HAVE_SCHED_CLOCK
550 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
553 bool "Micrel/Kendin KS8695"
555 select ARCH_REQUIRE_GPIOLIB
556 select ARCH_USES_GETTIMEOFFSET
558 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
559 System-on-Chip devices.
562 bool "NetSilicon NS9xxx"
565 select GENERIC_CLOCKEVENTS
568 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
571 <http://www.digi.com/products/microprocessors/index.jsp>
574 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
580 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
581 At present, the w90x900 has been renamed nuc900, regarding
582 the ARM series product line, you can login the following
583 link address to know more.
585 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
586 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
589 bool "Nuvoton NUC93X CPU"
593 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
594 low-power and high performance MPEG-4/JPEG multimedia controller chip.
600 select GENERIC_CLOCKEVENTS
603 select HAVE_SCHED_CLOCK
604 select ARCH_HAS_BARRIERS if CACHE_L2X0
605 select ARCH_HAS_CPUFREQ
607 This enables support for NVIDIA Tegra based systems (Tegra APX,
608 Tegra 6xx and Tegra 2 series).
611 bool "Philips Nexperia PNX4008 Mobile"
614 select ARCH_USES_GETTIMEOFFSET
616 This enables support for Philips PNX4008 mobile platform.
619 bool "PXA2xx/PXA3xx-based"
622 select ARCH_HAS_CPUFREQ
624 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
626 select HAVE_SCHED_CLOCK
631 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
636 select GENERIC_CLOCKEVENTS
637 select ARCH_REQUIRE_GPIOLIB
639 Support for Qualcomm MSM/QSD based systems. This runs on the
640 apps processor of the MSM/QSD and depends on a shared memory
641 interface to the modem processor which runs the baseband
642 stack and controls some vital subsystems
643 (clock and power control, etc).
646 bool "Renesas SH-Mobile / R-Mobile"
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
654 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
661 select ARCH_MAY_HAVE_PC_FDC
662 select HAVE_PATA_PLATFORM
665 select ARCH_SPARSEMEM_ENABLE
666 select ARCH_USES_GETTIMEOFFSET
668 On the Acorn Risc-PC, Linux can support the internal IDE disk and
669 CD-ROM interface, serial and parallel port, and the floppy drive.
675 select ARCH_SPARSEMEM_ENABLE
677 select ARCH_HAS_CPUFREQ
679 select GENERIC_CLOCKEVENTS
681 select HAVE_SCHED_CLOCK
683 select ARCH_REQUIRE_GPIOLIB
685 Support for StrongARM 11x0 based boards.
688 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
690 select ARCH_HAS_CPUFREQ
692 select ARCH_USES_GETTIMEOFFSET
693 select HAVE_S3C2410_I2C if I2C
695 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
696 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
697 the Samsung SMDK2410 development board (and derivatives).
699 Note, the S3C2416 and the S3C2450 are so close that they even share
700 the same SoC ID code. This means that there is no seperate machine
701 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
704 bool "Samsung S3C64XX"
710 select ARCH_USES_GETTIMEOFFSET
711 select ARCH_HAS_CPUFREQ
712 select ARCH_REQUIRE_GPIOLIB
713 select SAMSUNG_CLKSRC
714 select SAMSUNG_IRQ_VIC_TIMER
715 select SAMSUNG_IRQ_UART
716 select S3C_GPIO_TRACK
717 select S3C_GPIO_PULL_UPDOWN
718 select S3C_GPIO_CFG_S3C24XX
719 select S3C_GPIO_CFG_S3C64XX
721 select USB_ARCH_HAS_OHCI
722 select SAMSUNG_GPIOLIB_4BIT
723 select HAVE_S3C2410_I2C if I2C
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
726 Samsung S3C64XX series based systems
729 bool "Samsung S5P6440 S5P6450"
733 select HAVE_S3C2410_WATCHDOG if WATCHDOG
734 select ARCH_USES_GETTIMEOFFSET
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C_RTC if RTC_CLASS
738 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
742 bool "Samsung S5P6442"
746 select ARCH_USES_GETTIMEOFFSET
747 select HAVE_S3C2410_WATCHDOG if WATCHDOG
749 Samsung S5P6442 CPU based systems
752 bool "Samsung S5PC100"
756 select ARM_L1_CACHE_SHIFT_6
757 select ARCH_USES_GETTIMEOFFSET
758 select HAVE_S3C2410_I2C if I2C
759 select HAVE_S3C_RTC if RTC_CLASS
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 Samsung S5PC100 series based systems
765 bool "Samsung S5PV210/S5PC110"
767 select ARCH_SPARSEMEM_ENABLE
770 select ARM_L1_CACHE_SHIFT_6
771 select ARCH_HAS_CPUFREQ
772 select ARCH_USES_GETTIMEOFFSET
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C_RTC if RTC_CLASS
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 Samsung S5PV210/S5PC110 series based systems
780 bool "Samsung S5PV310/S5PC210"
782 select ARCH_SPARSEMEM_ENABLE
785 select ARCH_HAS_CPUFREQ
786 select GENERIC_CLOCKEVENTS
787 select HAVE_S3C_RTC if RTC_CLASS
788 select HAVE_S3C2410_I2C if I2C
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
791 Samsung S5PV310 series based systems
800 select ARCH_USES_GETTIMEOFFSET
802 Support for the StrongARM based Digital DNARD machine, also known
803 as "Shark" (<http://www.shark-linux.de/shark.html>).
806 bool "Telechips TCC ARM926-based systems"
810 select GENERIC_CLOCKEVENTS
812 Support for Telechips TCC ARM926-based systems.
817 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
818 select ARCH_USES_GETTIMEOFFSET
820 Say Y here for systems based on one of the Sharp LH7A40X
821 System on a Chip processors. These CPUs include an ARM922T
822 core with a wide array of integrated devices for
823 hand-held and low-power applications.
826 bool "ST-Ericsson U300 Series"
829 select HAVE_SCHED_CLOCK
833 select GENERIC_CLOCKEVENTS
837 Support for ST-Ericsson U300 series mobile platforms.
840 bool "ST-Ericsson U8500 Series"
843 select GENERIC_CLOCKEVENTS
845 select ARCH_REQUIRE_GPIOLIB
846 select ARCH_HAS_CPUFREQ
848 Support for ST-Ericsson's Ux500 architecture
851 bool "STMicroelectronics Nomadik"
856 select GENERIC_CLOCKEVENTS
857 select ARCH_REQUIRE_GPIOLIB
859 Support for the Nomadik platform by ST-Ericsson
863 select GENERIC_CLOCKEVENTS
864 select ARCH_REQUIRE_GPIOLIB
868 select GENERIC_ALLOCATOR
869 select ARCH_HAS_HOLES_MEMORYMODEL
871 Support for TI's DaVinci platform.
876 select ARCH_REQUIRE_GPIOLIB
877 select ARCH_HAS_CPUFREQ
878 select GENERIC_CLOCKEVENTS
879 select HAVE_SCHED_CLOCK
880 select ARCH_HAS_HOLES_MEMORYMODEL
882 Support for TI's OMAP platform (OMAP1/2/3/4).
887 select ARCH_REQUIRE_GPIOLIB
889 select GENERIC_CLOCKEVENTS
892 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
895 bool "VIA/WonderMedia 85xx"
898 select ARCH_HAS_CPUFREQ
899 select GENERIC_CLOCKEVENTS
900 select ARCH_REQUIRE_GPIOLIB
903 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
907 # This is sorted alphabetically by mach-* pathname. However, plat-*
908 # Kconfigs may be included either alphabetically (according to the
909 # plat- suffix) or along side the corresponding mach-* source.
911 source "arch/arm/mach-aaec2000/Kconfig"
913 source "arch/arm/mach-at91/Kconfig"
915 source "arch/arm/mach-bcmring/Kconfig"
917 source "arch/arm/mach-clps711x/Kconfig"
919 source "arch/arm/mach-cns3xxx/Kconfig"
921 source "arch/arm/mach-davinci/Kconfig"
923 source "arch/arm/mach-dove/Kconfig"
925 source "arch/arm/mach-ep93xx/Kconfig"
927 source "arch/arm/mach-footbridge/Kconfig"
929 source "arch/arm/mach-gemini/Kconfig"
931 source "arch/arm/mach-h720x/Kconfig"
933 source "arch/arm/mach-integrator/Kconfig"
935 source "arch/arm/mach-iop32x/Kconfig"
937 source "arch/arm/mach-iop33x/Kconfig"
939 source "arch/arm/mach-iop13xx/Kconfig"
941 source "arch/arm/mach-ixp4xx/Kconfig"
943 source "arch/arm/mach-ixp2000/Kconfig"
945 source "arch/arm/mach-ixp23xx/Kconfig"
947 source "arch/arm/mach-kirkwood/Kconfig"
949 source "arch/arm/mach-ks8695/Kconfig"
951 source "arch/arm/mach-lh7a40x/Kconfig"
953 source "arch/arm/mach-loki/Kconfig"
955 source "arch/arm/mach-lpc32xx/Kconfig"
957 source "arch/arm/mach-msm/Kconfig"
959 source "arch/arm/mach-mv78xx0/Kconfig"
961 source "arch/arm/plat-mxc/Kconfig"
963 source "arch/arm/mach-mxs/Kconfig"
965 source "arch/arm/mach-netx/Kconfig"
967 source "arch/arm/mach-nomadik/Kconfig"
968 source "arch/arm/plat-nomadik/Kconfig"
970 source "arch/arm/mach-ns9xxx/Kconfig"
972 source "arch/arm/mach-nuc93x/Kconfig"
974 source "arch/arm/plat-omap/Kconfig"
976 source "arch/arm/mach-omap1/Kconfig"
978 source "arch/arm/mach-omap2/Kconfig"
980 source "arch/arm/mach-orion5x/Kconfig"
982 source "arch/arm/mach-pxa/Kconfig"
983 source "arch/arm/plat-pxa/Kconfig"
985 source "arch/arm/mach-mmp/Kconfig"
987 source "arch/arm/mach-realview/Kconfig"
989 source "arch/arm/mach-sa1100/Kconfig"
991 source "arch/arm/plat-samsung/Kconfig"
992 source "arch/arm/plat-s3c24xx/Kconfig"
993 source "arch/arm/plat-s5p/Kconfig"
995 source "arch/arm/plat-spear/Kconfig"
997 source "arch/arm/plat-tcc/Kconfig"
1000 source "arch/arm/mach-s3c2400/Kconfig"
1001 source "arch/arm/mach-s3c2410/Kconfig"
1002 source "arch/arm/mach-s3c2412/Kconfig"
1003 source "arch/arm/mach-s3c2416/Kconfig"
1004 source "arch/arm/mach-s3c2440/Kconfig"
1005 source "arch/arm/mach-s3c2443/Kconfig"
1009 source "arch/arm/mach-s3c64xx/Kconfig"
1012 source "arch/arm/mach-s5p64x0/Kconfig"
1014 source "arch/arm/mach-s5p6442/Kconfig"
1016 source "arch/arm/mach-s5pc100/Kconfig"
1018 source "arch/arm/mach-s5pv210/Kconfig"
1020 source "arch/arm/mach-s5pv310/Kconfig"
1022 source "arch/arm/mach-shmobile/Kconfig"
1024 source "arch/arm/plat-stmp3xxx/Kconfig"
1026 source "arch/arm/mach-tegra/Kconfig"
1028 source "arch/arm/mach-u300/Kconfig"
1030 source "arch/arm/mach-ux500/Kconfig"
1032 source "arch/arm/mach-versatile/Kconfig"
1034 source "arch/arm/mach-vexpress/Kconfig"
1036 source "arch/arm/mach-vt8500/Kconfig"
1038 source "arch/arm/mach-w90x900/Kconfig"
1040 # Definitions to make life easier
1046 select GENERIC_CLOCKEVENTS
1047 select HAVE_SCHED_CLOCK
1051 select HAVE_SCHED_CLOCK
1056 config PLAT_VERSATILE
1059 config ARM_TIMER_SP804
1062 source arch/arm/mm/Kconfig
1065 bool "Enable iWMMXt support"
1066 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1067 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1069 Enable support for iWMMXt context switching at run time if
1070 running on a CPU that supports it.
1072 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1075 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1079 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1080 (!ARCH_OMAP3 || OMAP3_EMU)
1084 config MULTI_IRQ_HANDLER
1087 Allow each machine to specify it's own IRQ handler at run time.
1090 source "arch/arm/Kconfig-nommu"
1093 config ARM_ERRATA_411920
1094 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1095 depends on CPU_V6 || CPU_V6K
1097 Invalidation of the Instruction Cache operation can
1098 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1099 It does not affect the MPCore. This option enables the ARM Ltd.
1100 recommended workaround.
1102 config ARM_ERRATA_430973
1103 bool "ARM errata: Stale prediction on replaced interworking branch"
1106 This option enables the workaround for the 430973 Cortex-A8
1107 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1108 interworking branch is replaced with another code sequence at the
1109 same virtual address, whether due to self-modifying code or virtual
1110 to physical address re-mapping, Cortex-A8 does not recover from the
1111 stale interworking branch prediction. This results in Cortex-A8
1112 executing the new code sequence in the incorrect ARM or Thumb state.
1113 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1114 and also flushes the branch target cache at every context switch.
1115 Note that setting specific bits in the ACTLR register may not be
1116 available in non-secure mode.
1118 config ARM_ERRATA_458693
1119 bool "ARM errata: Processor deadlock when a false hazard is created"
1122 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1123 erratum. For very specific sequences of memory operations, it is
1124 possible for a hazard condition intended for a cache line to instead
1125 be incorrectly associated with a different cache line. This false
1126 hazard might then cause a processor deadlock. The workaround enables
1127 the L1 caching of the NEON accesses and disables the PLD instruction
1128 in the ACTLR register. Note that setting specific bits in the ACTLR
1129 register may not be available in non-secure mode.
1131 config ARM_ERRATA_460075
1132 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1135 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1136 erratum. Any asynchronous access to the L2 cache may encounter a
1137 situation in which recent store transactions to the L2 cache are lost
1138 and overwritten with stale memory contents from external memory. The
1139 workaround disables the write-allocate mode for the L2 cache via the
1140 ACTLR register. Note that setting specific bits in the ACTLR register
1141 may not be available in non-secure mode.
1143 config ARM_ERRATA_742230
1144 bool "ARM errata: DMB operation may be faulty"
1145 depends on CPU_V7 && SMP
1147 This option enables the workaround for the 742230 Cortex-A9
1148 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1149 between two write operations may not ensure the correct visibility
1150 ordering of the two writes. This workaround sets a specific bit in
1151 the diagnostic register of the Cortex-A9 which causes the DMB
1152 instruction to behave as a DSB, ensuring the correct behaviour of
1155 config ARM_ERRATA_742231
1156 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1157 depends on CPU_V7 && SMP
1159 This option enables the workaround for the 742231 Cortex-A9
1160 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1161 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1162 accessing some data located in the same cache line, may get corrupted
1163 data due to bad handling of the address hazard when the line gets
1164 replaced from one of the CPUs at the same time as another CPU is
1165 accessing it. This workaround sets specific bits in the diagnostic
1166 register of the Cortex-A9 which reduces the linefill issuing
1167 capabilities of the processor.
1169 config PL310_ERRATA_588369
1170 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1171 depends on CACHE_L2X0
1173 The PL310 L2 cache controller implements three types of Clean &
1174 Invalidate maintenance operations: by Physical Address
1175 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1176 They are architecturally defined to behave as the execution of a
1177 clean operation followed immediately by an invalidate operation,
1178 both performing to the same memory location. This functionality
1179 is not correctly implemented in PL310 as clean lines are not
1180 invalidated as a result of these operations.
1182 config ARM_ERRATA_720789
1183 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1184 depends on CPU_V7 && SMP
1186 This option enables the workaround for the 720789 Cortex-A9 (prior to
1187 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1188 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1189 As a consequence of this erratum, some TLB entries which should be
1190 invalidated are not, resulting in an incoherency in the system page
1191 tables. The workaround changes the TLB flushing routines to invalidate
1192 entries regardless of the ASID.
1194 config PL310_ERRATA_727915
1195 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1196 depends on CACHE_L2X0
1198 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1199 operation (offset 0x7FC). This operation runs in background so that
1200 PL310 can handle normal accesses while it is in progress. Under very
1201 rare circumstances, due to this erratum, write data can be lost when
1202 PL310 treats a cacheable write transaction during a Clean &
1203 Invalidate by Way operation.
1205 config ARM_ERRATA_743622
1206 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1209 This option enables the workaround for the 743622 Cortex-A9
1210 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1211 optimisation in the Cortex-A9 Store Buffer may lead to data
1212 corruption. This workaround sets a specific bit in the diagnostic
1213 register of the Cortex-A9 which disables the Store Buffer
1214 optimisation, preventing the defect from occurring. This has no
1215 visible impact on the overall performance or power consumption of the
1218 config ARM_ERRATA_751472
1219 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1220 depends on CPU_V7 && SMP
1222 This option enables the workaround for the 751472 Cortex-A9 (prior
1223 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1224 completion of a following broadcasted operation if the second
1225 operation is received by a CPU before the ICIALLUIS has completed,
1226 potentially leading to corrupted entries in the cache or TLB.
1228 config ARM_ERRATA_753970
1229 bool "ARM errata: cache sync operation may be faulty"
1230 depends on CACHE_PL310
1232 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1234 Under some condition the effect of cache sync operation on
1235 the store buffer still remains when the operation completes.
1236 This means that the store buffer is always asked to drain and
1237 this prevents it from merging any further writes. The workaround
1238 is to replace the normal offset of cache sync operation (0x730)
1239 by another offset targeting an unmapped PL310 register 0x740.
1240 This has the same effect as the cache sync operation: store buffer
1241 drain and waiting for all buffers empty.
1243 config ARM_ERRATA_754322
1244 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1247 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1248 r3p*) erratum. A speculative memory access may cause a page table walk
1249 which starts prior to an ASID switch but completes afterwards. This
1250 can populate the micro-TLB with a stale entry which may be hit with
1251 the new ASID. This workaround places two dsb instructions in the mm
1252 switching code so that no page table walks can cross the ASID switch.
1254 config ARM_ERRATA_754327
1255 bool "ARM errata: no automatic Store Buffer drain"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 754327 Cortex-A9 (prior to
1259 r2p0) erratum. The Store Buffer does not have any automatic draining
1260 mechanism and therefore a livelock may occur if an external agent
1261 continuously polls a memory location waiting to observe an update.
1262 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1263 written polling loops from denying visibility of updates to memory.
1267 source "arch/arm/common/Kconfig"
1277 Find out whether you have ISA slots on your motherboard. ISA is the
1278 name of a bus system, i.e. the way the CPU talks to the other stuff
1279 inside your box. Other bus systems are PCI, EISA, MicroChannel
1280 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1281 newer boards don't support it. If you have ISA, say Y, otherwise N.
1283 # Select ISA DMA controller support
1288 # Select ISA DMA interface
1293 bool "PCI support" if MIGHT_HAVE_PCI
1295 Find out whether you have a PCI motherboard. PCI is the name of a
1296 bus system, i.e. the way the CPU talks to the other stuff inside
1297 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1298 VESA. If you have PCI, say Y, otherwise N.
1304 config PCI_NANOENGINE
1305 bool "BSE nanoEngine PCI support"
1306 depends on SA1100_NANOENGINE
1308 Enable PCI on the BSE nanoEngine board.
1313 # Select the host bridge type
1314 config PCI_HOST_VIA82C505
1316 depends on PCI && ARCH_SHARK
1319 config PCI_HOST_ITE8152
1321 depends on PCI && MACH_ARMCORE
1325 source "drivers/pci/Kconfig"
1327 source "drivers/pcmcia/Kconfig"
1331 menu "Kernel Features"
1333 source "kernel/time/Kconfig"
1336 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1337 depends on EXPERIMENTAL
1338 depends on CPU_V6K || CPU_V7
1339 depends on GENERIC_CLOCKEVENTS
1340 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1341 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1342 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1343 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1344 select USE_GENERIC_SMP_HELPERS
1345 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1347 This enables support for systems with more than one CPU. If you have
1348 a system with only one CPU, like most personal computers, say N. If
1349 you have a system with more than one CPU, say Y.
1351 If you say N here, the kernel will run on single and multiprocessor
1352 machines, but will use only one CPU of a multiprocessor machine. If
1353 you say Y here, the kernel will run on many, but not all, single
1354 processor machines. On a single processor machine, the kernel will
1355 run faster if you say N here.
1357 See also <file:Documentation/i386/IO-APIC.txt>,
1358 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1359 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1361 If you don't know what to do here, say N.
1364 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1365 depends on EXPERIMENTAL
1366 depends on SMP && !XIP_KERNEL
1369 SMP kernels contain instructions which fail on non-SMP processors.
1370 Enabling this option allows the kernel to modify itself to make
1371 these instructions safe. Disabling it allows about 1K of space
1374 If you don't know what to do here, say Y.
1380 This option enables support for the ARM system coherency unit
1387 This options enables support for the ARM timer and watchdog unit
1390 prompt "Memory split"
1393 Select the desired split between kernel and user memory.
1395 If you are not absolutely sure what you are doing, leave this
1399 bool "3G/1G user/kernel split"
1401 bool "2G/2G user/kernel split"
1403 bool "1G/3G user/kernel split"
1408 default 0x40000000 if VMSPLIT_1G
1409 default 0x80000000 if VMSPLIT_2G
1413 int "Maximum number of CPUs (2-32)"
1419 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1420 depends on SMP && HOTPLUG && EXPERIMENTAL
1421 depends on !ARCH_MSM
1423 Say Y here to experiment with turning CPUs off and on. CPUs
1424 can be controlled through /sys/devices/system/cpu.
1427 bool "Use local timer interrupts"
1430 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1432 Enable support for local timers on SMP platforms, rather then the
1433 legacy IPI broadcast method. Local timers allows the system
1434 accounting to be spread across the timer interval, preventing a
1435 "thundering herd" at every timer tick.
1437 source kernel/Kconfig.preempt
1441 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1442 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1443 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1444 default AT91_TIMER_HZ if ARCH_AT91
1445 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1448 config THUMB2_KERNEL
1449 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1450 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1452 select ARM_ASM_UNIFIED
1454 By enabling this option, the kernel will be compiled in
1455 Thumb-2 mode. A compiler/assembler that understand the unified
1456 ARM-Thumb syntax is needed.
1460 config THUMB2_AVOID_R_ARM_THM_JUMP11
1461 bool "Work around buggy Thumb-2 short branch relocations in gas"
1462 depends on THUMB2_KERNEL && MODULES
1465 Various binutils versions can resolve Thumb-2 branches to
1466 locally-defined, preemptible global symbols as short-range "b.n"
1467 branch instructions.
1469 This is a problem, because there's no guarantee the final
1470 destination of the symbol, or any candidate locations for a
1471 trampoline, are within range of the branch. For this reason, the
1472 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1473 relocation in modules at all, and it makes little sense to add
1476 The symptom is that the kernel fails with an "unsupported
1477 relocation" error when loading some modules.
1479 Until fixed tools are available, passing
1480 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1481 code which hits this problem, at the cost of a bit of extra runtime
1482 stack usage in some cases.
1484 The problem is described in more detail at:
1485 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1487 Only Thumb-2 kernels are affected.
1489 Unless you are sure your tools don't have this problem, say Y.
1491 config ARM_ASM_UNIFIED
1495 bool "Use the ARM EABI to compile the kernel"
1497 This option allows for the kernel to be compiled using the latest
1498 ARM ABI (aka EABI). This is only useful if you are using a user
1499 space environment that is also compiled with EABI.
1501 Since there are major incompatibilities between the legacy ABI and
1502 EABI, especially with regard to structure member alignment, this
1503 option also changes the kernel syscall calling convention to
1504 disambiguate both ABIs and allow for backward compatibility support
1505 (selected with CONFIG_OABI_COMPAT).
1507 To use this you need GCC version 4.0.0 or later.
1510 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1511 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1514 This option preserves the old syscall interface along with the
1515 new (ARM EABI) one. It also provides a compatibility layer to
1516 intercept syscalls that have structure arguments which layout
1517 in memory differs between the legacy ABI and the new ARM EABI
1518 (only for non "thumb" binaries). This option adds a tiny
1519 overhead to all syscalls and produces a slightly larger kernel.
1520 If you know you'll be using only pure EABI user space then you
1521 can say N here. If this option is not selected and you attempt
1522 to execute a legacy ABI binary then the result will be
1523 UNPREDICTABLE (in fact it can be predicted that it won't work
1524 at all). If in doubt say Y.
1526 config ARCH_HAS_HOLES_MEMORYMODEL
1529 config ARCH_SPARSEMEM_ENABLE
1532 config ARCH_SPARSEMEM_DEFAULT
1533 def_bool ARCH_SPARSEMEM_ENABLE
1535 config ARCH_SELECT_MEMORY_MODEL
1536 def_bool ARCH_SPARSEMEM_ENABLE
1539 bool "High Memory Support (EXPERIMENTAL)"
1540 depends on MMU && EXPERIMENTAL
1542 The address space of ARM processors is only 4 Gigabytes large
1543 and it has to accommodate user address space, kernel address
1544 space as well as some memory mapped IO. That means that, if you
1545 have a large amount of physical memory and/or IO, not all of the
1546 memory can be "permanently mapped" by the kernel. The physical
1547 memory that is not permanently mapped is called "high memory".
1549 Depending on the selected kernel/user memory split, minimum
1550 vmalloc space and actual amount of RAM, you may not need this
1551 option which should result in a slightly faster kernel.
1556 bool "Allocate 2nd-level pagetables from highmem"
1558 depends on !OUTER_CACHE
1560 config HW_PERF_EVENTS
1561 bool "Enable hardware performance counter support for perf events"
1562 depends on PERF_EVENTS && CPU_HAS_PMU
1565 Enable hardware performance counter support for perf events. If
1566 disabled, perf events will use software events only.
1570 config FORCE_MAX_ZONEORDER
1571 int "Maximum zone order" if ARCH_SHMOBILE
1572 range 11 64 if ARCH_SHMOBILE
1573 default "9" if SA1111
1576 The kernel memory allocator divides physically contiguous memory
1577 blocks into "zones", where each zone is a power of two number of
1578 pages. This option selects the largest power of two that the kernel
1579 keeps in the memory allocator. If you need to allocate very large
1580 blocks of physically contiguous memory, then you may need to
1581 increase this value.
1583 This config option is actually maximum order plus one. For example,
1584 a value of 11 means that the largest free memory block is 2^10 pages.
1587 bool "Timer and CPU usage LEDs"
1588 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1589 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1590 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1591 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1592 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1593 ARCH_AT91 || ARCH_DAVINCI || \
1594 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1596 If you say Y here, the LEDs on your machine will be used
1597 to provide useful information about your current system status.
1599 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1600 be able to select which LEDs are active using the options below. If
1601 you are compiling a kernel for the EBSA-110 or the LART however, the
1602 red LED will simply flash regularly to indicate that the system is
1603 still functional. It is safe to say Y here if you have a CATS
1604 system, but the driver will do nothing.
1607 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1608 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1609 || MACH_OMAP_PERSEUS2
1611 depends on !GENERIC_CLOCKEVENTS
1612 default y if ARCH_EBSA110
1614 If you say Y here, one of the system LEDs (the green one on the
1615 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1616 will flash regularly to indicate that the system is still
1617 operational. This is mainly useful to kernel hackers who are
1618 debugging unstable kernels.
1620 The LART uses the same LED for both Timer LED and CPU usage LED
1621 functions. You may choose to use both, but the Timer LED function
1622 will overrule the CPU usage LED.
1625 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1627 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1628 || MACH_OMAP_PERSEUS2
1631 If you say Y here, the red LED will be used to give a good real
1632 time indication of CPU usage, by lighting whenever the idle task
1633 is not currently executing.
1635 The LART uses the same LED for both Timer LED and CPU usage LED
1636 functions. You may choose to use both, but the Timer LED function
1637 will overrule the CPU usage LED.
1639 config ALIGNMENT_TRAP
1641 depends on CPU_CP15_MMU
1642 default y if !ARCH_EBSA110
1643 select HAVE_PROC_CPU if PROC_FS
1645 ARM processors cannot fetch/store information which is not
1646 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1647 address divisible by 4. On 32-bit ARM processors, these non-aligned
1648 fetch/store instructions will be emulated in software if you say
1649 here, which has a severe performance impact. This is necessary for
1650 correct operation of some network protocols. With an IP-only
1651 configuration it is safe to say N, otherwise say Y.
1653 config UACCESS_WITH_MEMCPY
1654 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1655 depends on MMU && EXPERIMENTAL
1656 default y if CPU_FEROCEON
1658 Implement faster copy_to_user and clear_user methods for CPU
1659 cores where a 8-word STM instruction give significantly higher
1660 memory write throughput than a sequence of individual 32bit stores.
1662 A possible side effect is a slight increase in scheduling latency
1663 between threads sharing the same address space if they invoke
1664 such copy operations with large buffers.
1666 However, if the CPU data cache is using a write-allocate mode,
1667 this option is unlikely to provide any performance gain.
1671 prompt "Enable seccomp to safely compute untrusted bytecode"
1673 This kernel feature is useful for number crunching applications
1674 that may need to compute untrusted bytecode during their
1675 execution. By using pipes or other transports made available to
1676 the process as file descriptors supporting the read/write
1677 syscalls, it's possible to isolate those applications in
1678 their own address space using seccomp. Once seccomp is
1679 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1680 and the task is only allowed to execute a few safe syscalls
1681 defined by each seccomp mode.
1683 config CC_STACKPROTECTOR
1684 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1685 depends on EXPERIMENTAL
1687 This option turns on the -fstack-protector GCC feature. This
1688 feature puts, at the beginning of functions, a canary value on
1689 the stack just before the return address, and validates
1690 the value just before actually returning. Stack based buffer
1691 overflows (that need to overwrite this return address) now also
1692 overwrite the canary, which gets detected and the attack is then
1693 neutralized via a kernel panic.
1694 This feature requires gcc version 4.2 or above.
1696 config DEPRECATED_PARAM_STRUCT
1697 bool "Provide old way to pass kernel parameters"
1699 This was deprecated in 2001 and announced to live on for 5 years.
1700 Some old boot loaders still use this way.
1706 # Compressed boot loader in ROM. Yes, we really want to ask about
1707 # TEXT and BSS so we preserve their values in the config files.
1708 config ZBOOT_ROM_TEXT
1709 hex "Compressed ROM boot loader base address"
1712 The physical address at which the ROM-able zImage is to be
1713 placed in the target. Platforms which normally make use of
1714 ROM-able zImage formats normally set this to a suitable
1715 value in their defconfig file.
1717 If ZBOOT_ROM is not enabled, this has no effect.
1719 config ZBOOT_ROM_BSS
1720 hex "Compressed ROM boot loader BSS address"
1723 The base address of an area of read/write memory in the target
1724 for the ROM-able zImage which must be available while the
1725 decompressor is running. It must be large enough to hold the
1726 entire decompressed kernel plus an additional 128 KiB.
1727 Platforms which normally make use of ROM-able zImage formats
1728 normally set this to a suitable value in their defconfig file.
1730 If ZBOOT_ROM is not enabled, this has no effect.
1733 bool "Compressed boot loader in ROM/flash"
1734 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1736 Say Y here if you intend to execute your compressed kernel image
1737 (zImage) directly from ROM or flash. If unsure, say N.
1739 config ZBOOT_ROM_MMCIF
1740 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1741 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1743 Say Y here to include experimental MMCIF loading code in the
1744 ROM-able zImage. With this enabled it is possible to write the
1745 the ROM-able zImage kernel image to an MMC card and boot the
1746 kernel straight from the reset vector. At reset the processor
1747 Mask ROM will load the first part of the the ROM-able zImage
1748 which in turn loads the rest the kernel image to RAM using the
1749 MMCIF hardware block.
1752 string "Default kernel command string"
1755 On some architectures (EBSA110 and CATS), there is currently no way
1756 for the boot loader to pass arguments to the kernel. For these
1757 architectures, you should supply some command-line options at build
1758 time by entering them here. As a minimum, you should specify the
1759 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1761 config CMDLINE_FORCE
1762 bool "Always use the default kernel command string"
1763 depends on CMDLINE != ""
1765 Always use the default kernel command string, even if the boot
1766 loader passes other arguments to the kernel.
1767 This is useful if you cannot or don't want to change the
1768 command-line options your boot loader passes to the kernel.
1773 bool "Kernel Execute-In-Place from ROM"
1774 depends on !ZBOOT_ROM
1776 Execute-In-Place allows the kernel to run from non-volatile storage
1777 directly addressable by the CPU, such as NOR flash. This saves RAM
1778 space since the text section of the kernel is not loaded from flash
1779 to RAM. Read-write sections, such as the data section and stack,
1780 are still copied to RAM. The XIP kernel is not compressed since
1781 it has to run directly from flash, so it will take more space to
1782 store it. The flash address used to link the kernel object files,
1783 and for storing it, is configuration dependent. Therefore, if you
1784 say Y here, you must know the proper physical address where to
1785 store the kernel image depending on your own flash memory usage.
1787 Also note that the make target becomes "make xipImage" rather than
1788 "make zImage" or "make Image". The final kernel binary to put in
1789 ROM memory will be arch/arm/boot/xipImage.
1793 config XIP_PHYS_ADDR
1794 hex "XIP Kernel Physical Location"
1795 depends on XIP_KERNEL
1796 default "0x00080000"
1798 This is the physical address in your flash memory the kernel will
1799 be linked for and stored to. This address is dependent on your
1803 bool "Kexec system call (EXPERIMENTAL)"
1804 depends on EXPERIMENTAL
1806 kexec is a system call that implements the ability to shutdown your
1807 current kernel, and to start another kernel. It is like a reboot
1808 but it is independent of the system firmware. And like a reboot
1809 you can start any kernel with it, not just Linux.
1811 It is an ongoing process to be certain the hardware in a machine
1812 is properly shutdown, so do not be surprised if this code does not
1813 initially work for you. It may help to enable device hotplugging
1817 bool "Export atags in procfs"
1821 Should the atags used to boot the kernel be exported in an "atags"
1822 file in procfs. Useful with kexec.
1825 bool "Build kdump crash kernel (EXPERIMENTAL)"
1826 depends on EXPERIMENTAL
1828 Generate crash dump after being started by kexec. This should
1829 be normally only set in special crash dump kernels which are
1830 loaded in the main kernel with kexec-tools into a specially
1831 reserved region and then later executed after a crash by
1832 kdump/kexec. The crash dump kernel must be compiled to a
1833 memory address not used by the main kernel
1835 For more details see Documentation/kdump/kdump.txt
1837 config AUTO_ZRELADDR
1838 bool "Auto calculation of the decompressed kernel image address"
1839 depends on !ZBOOT_ROM && !ARCH_U300
1841 ZRELADDR is the physical address where the decompressed kernel
1842 image will be placed. If AUTO_ZRELADDR is selected, the address
1843 will be determined at run-time by masking the current IP with
1844 0xf8000000. This assumes the zImage being placed in the first 128MB
1845 from start of memory.
1849 menu "CPU Power Management"
1853 source "drivers/cpufreq/Kconfig"
1856 tristate "CPUfreq driver for i.MX CPUs"
1857 depends on ARCH_MXC && CPU_FREQ
1859 This enables the CPUfreq driver for i.MX CPUs.
1861 config CPU_FREQ_SA1100
1864 config CPU_FREQ_SA1110
1867 config CPU_FREQ_INTEGRATOR
1868 tristate "CPUfreq driver for ARM Integrator CPUs"
1869 depends on ARCH_INTEGRATOR && CPU_FREQ
1872 This enables the CPUfreq driver for ARM Integrator CPUs.
1874 For details, take a look at <file:Documentation/cpu-freq>.
1880 depends on CPU_FREQ && ARCH_PXA && PXA25x
1882 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1884 config CPU_FREQ_S3C64XX
1885 bool "CPUfreq support for Samsung S3C64XX CPUs"
1886 depends on CPU_FREQ && CPU_S3C6410
1891 Internal configuration node for common cpufreq on Samsung SoC
1893 config CPU_FREQ_S3C24XX
1894 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1895 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1898 This enables the CPUfreq driver for the Samsung S3C24XX family
1901 For details, take a look at <file:Documentation/cpu-freq>.
1905 config CPU_FREQ_S3C24XX_PLL
1906 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1907 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1909 Compile in support for changing the PLL frequency from the
1910 S3C24XX series CPUfreq driver. The PLL takes time to settle
1911 after a frequency change, so by default it is not enabled.
1913 This also means that the PLL tables for the selected CPU(s) will
1914 be built which may increase the size of the kernel image.
1916 config CPU_FREQ_S3C24XX_DEBUG
1917 bool "Debug CPUfreq Samsung driver core"
1918 depends on CPU_FREQ_S3C24XX
1920 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1922 config CPU_FREQ_S3C24XX_IODEBUG
1923 bool "Debug CPUfreq Samsung driver IO timing"
1924 depends on CPU_FREQ_S3C24XX
1926 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1928 config CPU_FREQ_S3C24XX_DEBUGFS
1929 bool "Export debugfs for CPUFreq"
1930 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1932 Export status information via debugfs.
1936 source "drivers/cpuidle/Kconfig"
1940 menu "Floating point emulation"
1942 comment "At least one emulation must be selected"
1945 bool "NWFPE math emulation"
1946 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1948 Say Y to include the NWFPE floating point emulator in the kernel.
1949 This is necessary to run most binaries. Linux does not currently
1950 support floating point hardware so you need to say Y here even if
1951 your machine has an FPA or floating point co-processor podule.
1953 You may say N here if you are going to load the Acorn FPEmulator
1954 early in the bootup.
1957 bool "Support extended precision"
1958 depends on FPE_NWFPE
1960 Say Y to include 80-bit support in the kernel floating-point
1961 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1962 Note that gcc does not generate 80-bit operations by default,
1963 so in most cases this option only enlarges the size of the
1964 floating point emulator without any good reason.
1966 You almost surely want to say N here.
1969 bool "FastFPE math emulation (EXPERIMENTAL)"
1970 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1972 Say Y here to include the FAST floating point emulator in the kernel.
1973 This is an experimental much faster emulator which now also has full
1974 precision for the mantissa. It does not support any exceptions.
1975 It is very simple, and approximately 3-6 times faster than NWFPE.
1977 It should be sufficient for most programs. It may be not suitable
1978 for scientific calculations, but you have to check this for yourself.
1979 If you do not feel you need a faster FP emulation you should better
1983 bool "VFP-format floating point maths"
1984 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1986 Say Y to include VFP support code in the kernel. This is needed
1987 if your hardware includes a VFP unit.
1989 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1990 release notes and additional status information.
1992 Say N if your target does not have VFP hardware.
2000 bool "Advanced SIMD (NEON) Extension support"
2001 depends on VFPv3 && CPU_V7
2003 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2008 menu "Userspace binary formats"
2010 source "fs/Kconfig.binfmt"
2013 tristate "RISC OS personality"
2016 Say Y here to include the kernel code necessary if you want to run
2017 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2018 experimental; if this sounds frightening, say N and sleep in peace.
2019 You can also say M here to compile this support as a module (which
2020 will be called arthur).
2024 menu "Power management options"
2026 source "kernel/power/Kconfig"
2028 config ARCH_SUSPEND_POSSIBLE
2033 source "net/Kconfig"
2035 source "drivers/Kconfig"
2039 source "arch/arm/Kconfig.debug"
2041 source "security/Kconfig"
2043 source "crypto/Kconfig"
2045 source "lib/Kconfig"