2 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARC
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 * -Userspace unaligned access emulation
13 * vineetg: Feb 2011 (ptrace low level code fixes)
14 * -traced syscall return code (r0) was not saved into pt_regs for restoring
15 * into user reg-file when traded task rets to user space.
16 * -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
17 * were not invoking post-syscall trace hook (jumping directly into
18 * ret_from_system_call)
21 * -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
22 * -To maintain the slot size of 8 bytes/vector, added nop, which is
23 * not executed at runtime.
25 * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
26 * -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
27 * -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
31 * -In a rare scenario, Process gets a Priv-V exception and gets scheduled
32 * out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
33 * active (AE bit enabled). This causes a double fault for a subseq valid
34 * exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
35 * Instr Error could also cause similar scenario, so same there as well.
37 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
39 * Vineetg: Aug 28th 2008: Bug #94984
40 * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
41 * Normally CPU does this automatically, however when doing FAKE rtie,
42 * we need to explicitly do this. The problem in macros
43 * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
44 * was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
45 * setting it and not clearing it clears ZOL context
47 * Vineetg: May 16th, 2008
48 * - r25 now contains the Current Task when in kernel
50 * Vineetg: Dec 22, 2007
51 * Minor Surgery of Low Level ISR to make it SMP safe
52 * - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
53 * - _current_task is made an array of NR_CPUS
54 * - Access of _current_task wrapped inside a macro so that if hardware
55 * team agrees for a dedicated reg, no other code is touched
57 * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
60 /*------------------------------------------------------------------
62 *------------------------------------------------------------------
65 * Caller Saved Registers r0 - r12
66 * Callee Saved Registers r13- r25
67 * Global Pointer (gp) r26
68 * Frame Pointer (fp) r27
69 * Stack Pointer (sp) r28
70 * Interrupt link register (ilink1) r29
71 * Interrupt link register (ilink2) r30
72 * Branch link register (blink) r31
73 *------------------------------------------------------------------
78 ;############################ Vector Table #################################
81 #if 1 /* Just in case, build breaks */
89 .section .vector, "ax",@progbits
92 /* Each entry in the vector table must occupy 2 words. Since it is a jump
93 * across sections (.vector to .text) we are gauranteed that 'j somewhere'
94 * will use the 'j limm' form of the intrsuction as long as somewhere is in
95 * a section other than .vector.
98 ; ********* Critical System Events **********************
99 VECTOR res_service ; 0x0, Restart Vector (0x0)
100 VECTOR mem_service ; 0x8, Mem exception (0x1)
101 VECTOR instr_service ; 0x10, Instrn Error (0x2)
103 ; ******************** Device ISRs **********************
104 #ifdef CONFIG_ARC_IRQ3_LV2
105 VECTOR handle_interrupt_level2
107 VECTOR handle_interrupt_level1
110 VECTOR handle_interrupt_level1
112 #ifdef CONFIG_ARC_IRQ5_LV2
113 VECTOR handle_interrupt_level2
115 VECTOR handle_interrupt_level1
118 #ifdef CONFIG_ARC_IRQ6_LV2
119 VECTOR handle_interrupt_level2
121 VECTOR handle_interrupt_level1
125 VECTOR handle_interrupt_level1 ; Other devices
128 /* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
130 ; ******************** Exceptions **********************
131 VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
132 VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
133 VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
134 VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
135 ; or Misaligned Access
136 VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
137 VECTOR EV_Trap ; 0x128, Trap exception (0x25)
138 VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
141 VECTOR reserved ; Reserved Exceptions
144 #include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
145 #include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
146 #include <asm/errno.h>
147 #include <asm/arcregs.h>
148 #include <asm/irqflags.h>
150 ;##################### Scratch Mem for IRQ stack switching #############
152 ARCFP_DATA int1_saved_reg
154 .type int1_saved_reg, @object
155 .size int1_saved_reg, 4
159 /* Each Interrupt level needs it's own scratch */
160 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
162 ARCFP_DATA int2_saved_reg
163 .type int2_saved_reg, @object
164 .size int2_saved_reg, 4
170 ; ---------------------------------------------
171 .section .text, "ax",@progbits
173 res_service: ; processor restart
174 flag 0x1 ; not implemented
178 reserved: ; processor restart
179 rtie ; jump to processor initializations
181 ;##################### Interrupt Handling ##############################
183 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
184 ; ---------------------------------------------
185 ; Level 2 ISR: Can interrupt a Level 1 ISR
186 ; ---------------------------------------------
187 ARC_ENTRY handle_interrupt_level2
189 ; TODO-vineetg for SMP this wont work
190 ; free up r9 as scratchpad
191 st r9, [@int2_saved_reg]
193 ;Which mode (user/kernel) was the system in when intr occured
199 ;------------------------------------------------------
200 ; if L2 IRQ interrupted a L1 ISR, disable preemption
201 ;------------------------------------------------------
203 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
204 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
206 ; A1 is set in status32_l2
207 ; bump thread_info->preempt_count (Disable preemption)
208 GET_CURR_THR_INFO_FROM_SP r10
209 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
211 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
214 ;------------------------------------------------------
215 ; setup params for Linux common ISR and invoke it
216 ;------------------------------------------------------
224 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
228 ARC_EXIT handle_interrupt_level2
232 ; ---------------------------------------------
234 ; ---------------------------------------------
235 ARC_ENTRY handle_interrupt_level1
237 /* free up r9 as scratchpad */
239 sr r9, [ARC_REG_SCRATCH_DATA0]
241 st r9, [@int1_saved_reg]
244 ;Which mode (user/kernel) was the system in when intr occured
257 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
260 ARC_EXIT handle_interrupt_level1
262 ;################### Non TLB Exception Handling #############################
264 ; ---------------------------------------------
265 ; Instruction Error Exception Handler
266 ; ---------------------------------------------
268 ARC_ENTRY instr_service
270 EXCPN_PROLOG_FREEUP_REG r9
282 FAKE_RET_FROM_EXCPN r9
284 bl do_insterror_or_kprobe
286 ARC_EXIT instr_service
288 ; ---------------------------------------------
289 ; Memory Error Exception Handler
290 ; ---------------------------------------------
292 ARC_ENTRY mem_service
294 EXCPN_PROLOG_FREEUP_REG r9
308 ; ---------------------------------------------
309 ; Machine Check Exception Handler
310 ; ---------------------------------------------
312 ARC_ENTRY EV_MachineCheck
314 EXCPN_PROLOG_FREEUP_REG r9
326 brne r3, ECR_C_MCHK_DUP_TLB, 1f
328 bl do_tlb_overlap_fault
332 ; DEAD END: can't do much, display Regs and HALT
333 SAVE_CALLEE_SAVED_USER
335 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
336 st sp, [r10, THREAD_CALLEE_REG]
338 j do_machine_check_fault
340 ARC_EXIT EV_MachineCheck
342 ; ---------------------------------------------
343 ; Protection Violation Exception Handler
344 ; ---------------------------------------------
346 ARC_ENTRY EV_TLBProtV
348 EXCPN_PROLOG_FREEUP_REG r9
350 ;Which mode (user/kernel) was the system in when Exception occured
356 ;---------(3) Save some more regs-----------------
357 ; vineetg: Mar 6th: Random Seg Fault issue #1
358 ; ecr and efa were not saved in case an Intr sneaks in
362 lr r1, [efa] ; Faulting Data address
364 ; --------(4) Return from CPU Exception Mode ---------
365 ; Fake a rtie, but rtie to next label
366 ; That way, subsequently, do_page_fault ( ) executes in pure kernel
367 ; mode with further Exceptions enabled
369 FAKE_RET_FROM_EXCPN r9
371 ;------ (5) Type of Protection Violation? ----------
373 ; ProtV Hardware Exception is triggered for Access Faults of 2 types
374 ; -Access Violaton : 00_23_(00|01|02|03)_00
376 ; -Unaligned Access : 00_23_04_00
378 bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
380 ;========= (6a) Access Violation Processing ========
385 ;========== (6b) Non aligned access ============
387 mov r0, r2 ; cause code
390 #ifdef CONFIG_ARC_MISALIGN_ACCESS
391 SAVE_CALLEE_SAVED_USER
392 mov r3, sp ; callee_regs
394 bl do_misaligned_access
396 ; TBD: optimize - do this only if a callee reg was involved
397 ; either a dst of emulated LD/ST or src with address-writeback
398 RESTORE_CALLEE_SAVED_USER
400 bl do_misaligned_error
407 ; ---------------------------------------------
408 ; Privilege Violation Exception Handler
409 ; ---------------------------------------------
410 ARC_ENTRY EV_PrivilegeV
412 EXCPN_PROLOG_FREEUP_REG r9
423 FAKE_RET_FROM_EXCPN r9
425 bl do_privilege_fault
427 ARC_EXIT EV_PrivilegeV
429 ; ---------------------------------------------
430 ; Extension Instruction Exception Handler
431 ; ---------------------------------------------
432 ARC_ENTRY EV_Extension
434 EXCPN_PROLOG_FREEUP_REG r9
443 bl do_extension_fault
445 ARC_EXIT EV_Extension
447 ;######################### System Call Tracing #########################
450 ; save EFA in case tracer wants the PC of traced task
451 ; using ERET won't work since next-PC has already committed
453 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
454 st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
456 ; PRE Sys Call Ptrace hook
457 mov r0, sp ; pt_regs needed
458 bl @syscall_trace_entry
460 ; Tracing code now returns the syscall num (orig or modif)
463 ; Do the Sys Call as we normally would.
464 ; Validate the Sys Call number
469 ; Restore the sys-call args. Mere invocation of the hook abv could have
470 ; clobbered them (since they are in scratch regs). The tracer could also
471 ; have deliberately changed the syscall args: r0-r7
480 ld.as r9, [sys_call_table, r8]
481 jl [r9] ; Entry into Sys Call Handler
484 st r0, [sp, PT_r0] ; sys call return value in pt_regs
486 ;POST Sys Call Ptrace Hook
487 bl @syscall_trace_exit
488 b ret_from_exception ; NOT ret_from_system_call at is saves r0 which
489 ; we'd done before calling post hook above
491 ;################### Break Point TRAP ##########################
493 ; ======= (5b) Trap is due to Break-Point =========
497 ; stop_pc info by gdb needs this info
498 stw orig_r8_IS_BRKPT, [sp, PT_orig_r8]
504 ; Now that we have read EFA, its safe to do "fake" rtie
505 ; and get out of CPU exception mode
506 FAKE_RET_FROM_EXCPN r11
508 ; Save callee regs in case gdb wants to have a look
509 ; SP will grow up by size of CALLEE Reg-File
511 SAVE_CALLEE_SAVED_USER
513 ; save location of saved Callee Regs @ thread_struct->pc
514 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
515 st sp, [r10, THREAD_CALLEE_REG]
517 ; Call the trap handler
520 ; unwind stack to discard Callee saved Regs
521 DISCARD_CALLEE_SAVED_USER
525 ;##################### Trap Handling ##############################
527 ; EV_Trap caused by TRAP_S and TRAP0 instructions.
528 ;------------------------------------------------------------------
530 ; :parameters in r0-r7.
531 ; :r8 has the system call number
533 ;------------------------------------------------------------------
537 ; Need at least 1 reg to code the early exception prolog
538 EXCPN_PROLOG_FREEUP_REG r9
540 ;Which mode (user/kernel) was the system in when intr occured
546 ;------- (4) What caused the Trap --------------
551 ; ======= (5a) Trap is due to System Call ========
553 ; Before doing anything, return from CPU Exception Mode
554 FAKE_RET_FROM_EXCPN r11
556 ; If syscall tracing ongoing, invoke pre-pos-hooks
557 GET_CURR_THR_INFO_FLAGS r10
558 btst r10, TIF_SYSCALL_TRACE
559 bnz tracesys ; this never comes back
561 ;============ This is normal System Call case ==========
562 ; Sys-call num shd not exceed the total system calls avail
565 bhi ret_from_system_call
567 ; Offset into the syscall_table and call handler
568 ld.as r9,[sys_call_table, r8]
569 jl [r9] ; Entry into Sys Call Handler
571 ; fall through to ret_from_system_call
574 ARC_ENTRY ret_from_system_call
576 st r0, [sp, PT_r0] ; sys call return value in pt_regs
578 ; fall through yet again to ret_from_exception
580 ;############# Return from Intr/Excp/Trap (Linux Specifics) ##############
582 ; If ret to user mode do we need to handle signals, schedule() et al.
584 ARC_ENTRY ret_from_exception
586 ; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32
587 ld r8, [sp, PT_status32] ; returning to User/Kernel Mode
589 #ifdef CONFIG_PREEMPT
590 bbit0 r8, STATUS_U_BIT, resume_kernel_mode
592 bbit0 r8, STATUS_U_BIT, restore_regs
595 ; Before returning to User mode check-for-and-complete any pending work
596 ; such as rescheduling/signal-delivery etc.
597 resume_user_mode_begin:
599 ; Disable IRQs to ensures that chk for pending work itself is atomic
600 ; (and we don't end up missing a NEED_RESCHED/SIGPENDING due to an
604 ; Fast Path return to user mode if no pending work
605 GET_CURR_THR_INFO_FLAGS r9
606 and.f 0, r9, _TIF_WORK_MASK
609 ; --- (Slow Path #1) task preemption ---
610 bbit0 r9, TIF_NEED_RESCHED, .Lchk_pend_signals
611 mov blink, resume_user_mode_begin ; tail-call to U mode ret chks
612 b @schedule ; BTST+Bnz causes relo error in link
617 ; --- (Slow Path #2) pending signal ---
618 mov r0, sp ; pt_regs for arg to do_signal()/do_notify_resume()
620 bbit0 r9, TIF_SIGPENDING, .Lchk_notify_resume
622 ; Normal Trap/IRQ entry only saves Scratch (caller-saved) regs
623 ; in pt_reg since the "C" ABI (kernel code) will automatically
624 ; save/restore callee-saved regs.
626 ; However, here we need to explicitly save callee regs because
627 ; (i) If this signal causes coredump - full regfile needed
628 ; (ii) If signal is SIGTRAP/SIGSTOP, task is being traced thus
629 ; tracer might call PEEKUSR(CALLEE reg)
631 ; NOTE: SP will grow up by size of CALLEE Reg-File
632 SAVE_CALLEE_SAVED_USER ; clobbers r12
634 ; save location of saved Callee Regs @ thread_struct->callee
635 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
636 st sp, [r10, THREAD_CALLEE_REG]
640 ; Ideally we want to discard the Callee reg above, however if this was
641 ; a tracing signal, tracer could have done a POKEUSR(CALLEE reg)
642 RESTORE_CALLEE_SAVED_USER
644 b resume_user_mode_begin ; loop back to start of U mode ret
646 ; --- (Slow Path #3) notify_resume ---
648 btst r9, TIF_NOTIFY_RESUME
649 blnz @do_notify_resume
650 b resume_user_mode_begin ; unconditionally back to U mode ret chks
651 ; for single exit point from this block
653 #ifdef CONFIG_PREEMPT
657 ; Can't preempt if preemption disabled
658 GET_CURR_THR_INFO_FROM_SP r10
659 ld r8, [r10, THREAD_INFO_PREEMPT_COUNT]
660 brne r8, 0, restore_regs
662 ; check if this task's NEED_RESCHED flag set
663 ld r9, [r10, THREAD_INFO_FLAGS]
664 bbit0 r9, TIF_NEED_RESCHED, restore_regs
669 bl preempt_schedule_irq
671 ; preempt_schedule_irq() always returns with IRQ disabled
676 ;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
678 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
679 ; IRQ shd definitely not happen between now and rtie
683 ; Disable Interrupts while restoring reg-file back
684 ; XXX can this be optimised out
685 IRQ_DISABLE_SAVE r9, r10 ;@r10 has prisitine (pre-disable) copy
687 #ifdef CONFIG_ARC_CURR_IN_REG
689 ; Earlier this used to be only for returning to user mode
690 ; However with 2 levels of IRQ this can also happen even if
693 brhs r9, VMALLOC_START, 8f
698 ; Restore REG File. In case multiple Events outstanding,
699 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
700 ; Note that we use realtime STATUS32 (not pt_regs->status32) to
703 ; if Returning from Exception
704 bbit0 r10, STATUS_AE_BIT, not_exception
708 ; Not Exception so maybe Interrupts (Level 1 or 2)
712 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
714 bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
716 ;------------------------------------------------------------------
717 ; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
718 ; so that sched doesnt move to new task, causing L1 to be delayed
719 ; undeterministically. Now that we've achieved that, lets reset
720 ; things to what they were, before returning from L2 context
721 ;----------------------------------------------------------------
723 ldw r9, [sp, PT_orig_r8] ; get orig_r8 to make sure it is
724 brne r9, orig_r8_IS_IRQ2, 149f ; infact a L2 ISR ret path
726 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
727 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
729 ; A1 is set in status32_l2
730 ; decrement thread_info->preempt_count (re-enable preemption)
731 GET_CURR_THR_INFO_FROM_SP r10
732 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
734 ; paranoid check, given A1 was active when A2 happened, preempt count
735 ; must not be 0 beccause we would have incremented it.
736 ; If this does happen we simply HALT as it means a BUG !!!
743 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
751 not_level2_interrupt:
755 bbit0 r10, STATUS_A1_BIT, not_level1_interrupt
763 not_level1_interrupt:
765 ;this case is for syscalls or Exceptions (with fake rtie)
768 debug_marker_syscall:
771 ARC_EXIT ret_from_exception
773 ARC_ENTRY ret_from_fork
774 ; when the forked child comes here from the __switch_to function
775 ; r0 has the last task pointer.
776 ; put last task in scheduler queue
779 ; If kernel thread, jump to it's entry-point
780 ld r9, [sp, PT_status32]
784 mov r0, r13 ; arg to payload
787 ; special case of kernel_thread entry point returning back due to
788 ; kernel_execve() - pretend return from syscall to ret to userland
790 ARC_EXIT ret_from_fork
792 ;################### Special Sys Call Wrappers ##########################
794 ARC_ENTRY sys_clone_wrapper
795 SAVE_CALLEE_SAVED_USER
797 DISCARD_CALLEE_SAVED_USER
799 GET_CURR_THR_INFO_FLAGS r10
800 btst r10, TIF_SYSCALL_TRACE
803 b ret_from_system_call
804 ARC_EXIT sys_clone_wrapper
806 #ifdef CONFIG_ARC_DW2_UNWIND
807 ; Workaround for bug 94179 (STAR ):
808 ; Despite -fasynchronous-unwind-tables, linker is not making dwarf2 unwinder
809 ; section (.debug_frame) as loadable. So we force it here.
810 ; This also fixes STAR 9000487933 where the prev-workaround (objcopy --setflag)
811 ; would not work after a clean build due to kernel build system dependencies.
812 .section .debug_frame, "wa",@progbits