2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef _ASM_ARC_ARCREGS_H
10 #define _ASM_ARC_ARCREGS_H
14 /* Build Configuration Registers */
15 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
16 #define ARC_REG_CRC_BCR 0x62
17 #define ARC_REG_DVFB_BCR 0x64
18 #define ARC_REG_EXTARITH_BCR 0x65
19 #define ARC_REG_VECBASE_BCR 0x68
20 #define ARC_REG_PERIBASE_BCR 0x69
21 #define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
22 #define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
23 #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
24 #define ARC_REG_TIMERS_BCR 0x75
25 #define ARC_REG_ICCM_BCR 0x78
26 #define ARC_REG_XY_MEM_BCR 0x79
27 #define ARC_REG_MAC_BCR 0x7a
28 #define ARC_REG_MUL_BCR 0x7b
29 #define ARC_REG_SWAP_BCR 0x7c
30 #define ARC_REG_NORM_BCR 0x7d
31 #define ARC_REG_MIXMAX_BCR 0x7e
32 #define ARC_REG_BARREL_BCR 0x7f
33 #define ARC_REG_D_UNCACH_BCR 0x6A
35 /* status32 Bits Positions */
36 #define STATUS_AE_BIT 5 /* Exception active */
37 #define STATUS_DE_BIT 6 /* PC is in delay slot */
38 #define STATUS_U_BIT 7 /* User/Kernel mode */
39 #define STATUS_L_BIT 12 /* Loop inhibit */
41 /* These masks correspond to the status word(STATUS_32) bits */
42 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
43 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
44 #define STATUS_U_MASK (1<<STATUS_U_BIT)
45 #define STATUS_L_MASK (1<<STATUS_L_BIT)
48 * ECR: Exception Cause Reg bits-n-pieces
49 * [23:16] = Exception Vector
50 * [15: 8] = Exception Cause Code
51 * [ 7: 0] = Exception Parameters (for certain types only)
53 #define ECR_VEC_MASK 0xff0000
54 #define ECR_CODE_MASK 0x00ff00
55 #define ECR_PARAM_MASK 0x0000ff
57 /* Exception Cause Vector Values */
58 #define ECR_V_INSN_ERR 0x02
59 #define ECR_V_MACH_CHK 0x20
60 #define ECR_V_ITLB_MISS 0x21
61 #define ECR_V_DTLB_MISS 0x22
62 #define ECR_V_PROTV 0x23
64 /* Protection Violation Exception Cause Code Values */
65 #define ECR_C_PROTV_INST_FETCH 0x00
66 #define ECR_C_PROTV_LOAD 0x01
67 #define ECR_C_PROTV_STORE 0x02
68 #define ECR_C_PROTV_XCHG 0x03
69 #define ECR_C_PROTV_MISALIG_DATA 0x04
71 #define ECR_C_BIT_PROTV_MISALIG_DATA 10
73 /* Machine Check Cause Code Values */
74 #define ECR_C_MCHK_DUP_TLB 0x01
76 /* DTLB Miss Exception Cause Code Values */
77 #define ECR_C_BIT_DTLB_LD_MISS 8
78 #define ECR_C_BIT_DTLB_ST_MISS 9
81 /* Auxiliary registers */
82 #define AUX_IDENTITY 4
83 #define AUX_INTR_VEC_BASE 0x25
87 * Floating Pt Registers
88 * Status regs are read-only (build-time) so need not be saved/restored
90 #define ARC_AUX_FP_STAT 0x300
91 #define ARC_AUX_DPFP_1L 0x301
92 #define ARC_AUX_DPFP_1H 0x302
93 #define ARC_AUX_DPFP_2L 0x303
94 #define ARC_AUX_DPFP_2H 0x304
95 #define ARC_AUX_DPFP_STAT 0x305
100 ******************************************************************
101 * Inline ASM macros to read/write AUX Regs
102 * Essentially invocation of lr/sr insns from "C"
107 #define read_aux_reg(reg) __builtin_arc_lr(reg)
109 /* gcc builtin sr needs reg param to be long immediate */
110 #define write_aux_reg(reg_immed, val) \
111 __builtin_arc_sr((unsigned int)val, reg_immed)
115 #define read_aux_reg(reg) \
117 unsigned int __ret; \
118 __asm__ __volatile__( \
126 * Aux Reg address is specified as long immediate by caller
128 * write_aux_reg(0x69, some_val);
129 * This generates tightest code.
131 #define write_aux_reg(reg_imm, val) \
133 __asm__ __volatile__( \
136 : "ir"(val), "i"(reg_imm)); \
140 * Aux Reg address is specified in a variable
143 * write_aux_reg2(reg_num, some_val);
144 * This has to generate glue code to load the reg num from
145 * memory to a reg hence not recommended.
147 #define write_aux_reg2(reg_in_var, val) \
151 __asm__ __volatile__( \
152 " ld %0, [%2] \n\t" \
153 " sr %1, [%0] \n\t" \
155 : "r"(val), "memory"(®_in_var)); \
160 #define READ_BCR(reg, into) \
163 tmp = read_aux_reg(reg); \
164 if (sizeof(tmp) == sizeof(into)) { \
165 into = *((typeof(into) *)&tmp); \
167 extern void bogus_undefined(void); \
172 #define WRITE_BCR(reg, into) \
175 if (sizeof(tmp) == sizeof(into)) { \
176 tmp = (*(unsigned int *)(into)); \
177 write_aux_reg(reg, tmp); \
179 extern void bogus_undefined(void); \
185 #define TO_KB(bytes) ((bytes) >> 10)
186 #define TO_MB(bytes) (TO_KB(bytes) >> 10)
187 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
188 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
190 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
191 /* These DPFP regs need to be saved/restored across ctx-sw */
200 ***************************************************************
201 * Build Configuration Registers, with encoded hardware config
203 struct bcr_identity {
204 #ifdef CONFIG_CPU_BIG_ENDIAN
205 unsigned int chip_id:16, cpu_id:8, family:8;
207 unsigned int family:8, cpu_id:8, chip_id:16;
211 #define EXTN_SWAP_VALID 0x1
212 #define EXTN_NORM_VALID 0x2
213 #define EXTN_MINMAX_VALID 0x2
214 #define EXTN_BARREL_VALID 0x2
217 #ifdef CONFIG_CPU_BIG_ENDIAN
218 unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
221 unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
226 /* DSP Options Ref Manual */
227 struct bcr_extn_mac_mul {
228 #ifdef CONFIG_CPU_BIG_ENDIAN
229 unsigned int pad:16, type:8, ver:8;
231 unsigned int ver:8, type:8, pad:16;
235 struct bcr_extn_xymem {
236 #ifdef CONFIG_CPU_BIG_ENDIAN
237 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
239 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
244 #ifdef CONFIG_CPU_BIG_ENDIAN
245 unsigned int start:8, pad2:8, sz:8, pad:8;
247 unsigned int pad:8, sz:8, pad2:8, start:8;
251 #ifdef CONFIG_CPU_BIG_ENDIAN
252 unsigned int base:16, pad:5, sz:3, ver:8;
254 unsigned int ver:8, sz:3, pad:5, base:16;
258 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
259 struct bcr_dccm_base {
260 #ifdef CONFIG_CPU_BIG_ENDIAN
261 unsigned int addr:24, ver:8;
263 unsigned int ver:8, addr:24;
267 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
269 #ifdef CONFIG_CPU_BIG_ENDIAN
270 unsigned int res:21, sz:3, ver:8;
272 unsigned int ver:8, sz:3, res:21;
276 /* Both SP and DP FPU BCRs have same format */
278 #ifdef CONFIG_CPU_BIG_ENDIAN
279 unsigned int fast:1, ver:8;
281 unsigned int ver:8, fast:1;
286 *******************************************************************
287 * Generic structures to hold build configuration used at runtime
290 struct cpuinfo_arc_mmu {
291 unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
294 struct cpuinfo_arc_cache {
295 unsigned int sz, line_len, assoc, ver;
298 struct cpuinfo_arc_ccm {
299 unsigned int base_addr, sz;
303 struct cpuinfo_arc_cache icache, dcache;
304 struct cpuinfo_arc_mmu mmu;
305 struct bcr_identity core;
307 unsigned int vec_base;
308 unsigned int uncached_base;
309 struct cpuinfo_arc_ccm iccm, dccm;
310 struct bcr_extn extn;
311 struct bcr_extn_xymem extn_xymem;
312 struct bcr_extn_mac_mul extn_mac_mul;
313 struct bcr_fp fp, dpfp;
316 extern struct cpuinfo_arc cpuinfo_arc700[];
318 #endif /* __ASEMBLY__ */
320 #endif /* __KERNEL__ */
322 #endif /* _ASM_ARC_ARCREGS_H */