4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
8 in the host1x address space. Should be 1.
9 - #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1.
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
19 The host1x top-level node defines a number of children, each representing one
20 of the following host1x client modules:
25 - compatible: "nvidia,tegra<chip>-mpe"
26 - reg: Physical base address and length of the controller's registers.
27 - interrupts: The interrupt outputs from the controller.
28 - clocks: Must contain one entry, for the module clock.
29 See ../clocks/clock-bindings.txt for details.
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
38 - compatible: "nvidia,tegra<chip>-vi"
39 - reg: Physical base address and length of the controller's registers.
40 - interrupts: The interrupt outputs from the controller.
41 - clocks: Must contain one entry, for the module clock.
42 See ../clocks/clock-bindings.txt for details.
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
48 - epp: encoder pre-processor
51 - compatible: "nvidia,tegra<chip>-epp"
52 - reg: Physical base address and length of the controller's registers.
53 - interrupts: The interrupt outputs from the controller.
54 - clocks: Must contain one entry, for the module clock.
55 See ../clocks/clock-bindings.txt for details.
56 - resets: Must contain an entry for each entry in reset-names.
57 See ../reset/reset.txt for details.
58 - reset-names: Must include the following entries:
61 - isp: image signal processor
64 - compatible: "nvidia,tegra<chip>-isp"
65 - reg: Physical base address and length of the controller's registers.
66 - interrupts: The interrupt outputs from the controller.
67 - clocks: Must contain one entry, for the module clock.
68 See ../clocks/clock-bindings.txt for details.
69 - resets: Must contain an entry for each entry in reset-names.
70 See ../reset/reset.txt for details.
71 - reset-names: Must include the following entries:
74 - gr2d: 2D graphics engine
77 - compatible: "nvidia,tegra<chip>-gr2d"
78 - reg: Physical base address and length of the controller's registers.
79 - interrupts: The interrupt outputs from the controller.
80 - clocks: Must contain one entry, for the module clock.
81 See ../clocks/clock-bindings.txt for details.
82 - resets: Must contain an entry for each entry in reset-names.
83 See ../reset/reset.txt for details.
84 - reset-names: Must include the following entries:
87 - gr3d: 3D graphics engine
90 - compatible: "nvidia,tegra<chip>-gr3d"
91 - reg: Physical base address and length of the controller's registers.
92 - clocks: Must contain an entry for each entry in clock-names.
93 See ../clocks/clock-bindings.txt for details.
94 - clock-names: Must include the following entries:
95 (This property may be omitted if the only clock in the list is "3d")
97 This MUST be the first entry.
98 - 3d2 (Only required on SoCs with two 3D clocks)
99 - resets: Must contain an entry for each entry in reset-names.
100 See ../reset/reset.txt for details.
101 - reset-names: Must include the following entries:
103 - 3d2 (Only required on SoCs with two 3D clocks)
105 - dc: display controller
108 - compatible: "nvidia,tegra<chip>-dc"
109 - reg: Physical base address and length of the controller's registers.
110 - interrupts: The interrupt outputs from the controller.
111 - clocks: Must contain an entry for each entry in clock-names.
112 See ../clocks/clock-bindings.txt for details.
113 - clock-names: Must include the following entries:
115 This MUST be the first entry.
117 - resets: Must contain an entry for each entry in reset-names.
118 See ../reset/reset.txt for details.
119 - reset-names: Must include the following entries:
122 Each display controller node has a child node, named "rgb", that represents
123 the RGB output associated with the controller. It can take the following
125 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
126 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
127 - nvidia,edid: supplies a binary EDID blob
129 - hdmi: High Definition Multimedia Interface
132 - compatible: "nvidia,tegra<chip>-hdmi"
133 - reg: Physical base address and length of the controller's registers.
134 - interrupts: The interrupt outputs from the controller.
135 - vdd-supply: regulator for supply voltage
136 - pll-supply: regulator for PLL
137 - clocks: Must contain an entry for each entry in clock-names.
138 See ../clocks/clock-bindings.txt for details.
139 - clock-names: Must include the following entries:
141 This MUST be the first entry.
143 - resets: Must contain an entry for each entry in reset-names.
144 See ../reset/reset.txt for details.
145 - reset-names: Must include the following entries:
149 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
150 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
151 - nvidia,edid: supplies a binary EDID blob
153 - tvo: TV encoder output
156 - compatible: "nvidia,tegra<chip>-tvo"
157 - reg: Physical base address and length of the controller's registers.
158 - interrupts: The interrupt outputs from the controller.
159 - clocks: Must contain one entry, for the module clock.
160 See ../clocks/clock-bindings.txt for details.
162 - dsi: display serial interface
165 - compatible: "nvidia,tegra<chip>-dsi"
166 - reg: Physical base address and length of the controller's registers.
167 - clocks: Must contain an entry for each entry in clock-names.
168 See ../clocks/clock-bindings.txt for details.
169 - clock-names: Must include the following entries:
171 This MUST be the first entry.
173 - resets: Must contain an entry for each entry in reset-names.
174 See ../reset/reset.txt for details.
175 - reset-names: Must include the following entries:
184 compatible = "nvidia,tegra20-host1x", "simple-bus";
185 reg = <0x50000000 0x00024000>;
186 interrupts = <0 65 0x04 /* mpcore syncpt */
187 0 67 0x04>; /* mpcore general */
188 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
189 resets = <&tegra_car 28>;
190 reset-names = "host1x";
192 #address-cells = <1>;
195 ranges = <0x54000000 0x54000000 0x04000000>;
198 compatible = "nvidia,tegra20-mpe";
199 reg = <0x54040000 0x00040000>;
200 interrupts = <0 68 0x04>;
201 clocks = <&tegra_car TEGRA20_CLK_MPE>;
202 resets = <&tegra_car 60>;
207 compatible = "nvidia,tegra20-vi";
208 reg = <0x54080000 0x00040000>;
209 interrupts = <0 69 0x04>;
210 clocks = <&tegra_car TEGRA20_CLK_VI>;
211 resets = <&tegra_car 100>;
216 compatible = "nvidia,tegra20-epp";
217 reg = <0x540c0000 0x00040000>;
218 interrupts = <0 70 0x04>;
219 clocks = <&tegra_car TEGRA20_CLK_EPP>;
220 resets = <&tegra_car 19>;
225 compatible = "nvidia,tegra20-isp";
226 reg = <0x54100000 0x00040000>;
227 interrupts = <0 71 0x04>;
228 clocks = <&tegra_car TEGRA20_CLK_ISP>;
229 resets = <&tegra_car 23>;
234 compatible = "nvidia,tegra20-gr2d";
235 reg = <0x54140000 0x00040000>;
236 interrupts = <0 72 0x04>;
237 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
238 resets = <&tegra_car 21>;
243 compatible = "nvidia,tegra20-gr3d";
244 reg = <0x54180000 0x00040000>;
245 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
246 resets = <&tegra_car 24>;
251 compatible = "nvidia,tegra20-dc";
252 reg = <0x54200000 0x00040000>;
253 interrupts = <0 73 0x04>;
254 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
255 <&tegra_car TEGRA20_CLK_PLL_P>;
256 clock-names = "disp1", "parent";
257 resets = <&tegra_car 27>;
266 compatible = "nvidia,tegra20-dc";
267 reg = <0x54240000 0x00040000>;
268 interrupts = <0 74 0x04>;
269 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
270 <&tegra_car TEGRA20_CLK_PLL_P>;
271 clock-names = "disp2", "parent";
272 resets = <&tegra_car 26>;
281 compatible = "nvidia,tegra20-hdmi";
282 reg = <0x54280000 0x00040000>;
283 interrupts = <0 75 0x04>;
284 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
285 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
286 clock-names = "hdmi", "parent";
287 resets = <&tegra_car 51>;
288 reset-names = "hdmi";
293 compatible = "nvidia,tegra20-tvo";
294 reg = <0x542c0000 0x00040000>;
295 interrupts = <0 76 0x04>;
296 clocks = <&tegra_car TEGRA20_CLK_TVO>;
301 compatible = "nvidia,tegra20-dsi";
302 reg = <0x54300000 0x00040000>;
303 clocks = <&tegra_car TEGRA20_CLK_DSI>,
304 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
305 clock-names = "dsi", "parent";
306 resets = <&tegra_car 48>;