4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
8 in the host1x address space. Should be 1.
9 - #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1.
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
19 The host1x top-level node defines a number of children, each representing one
20 of the following host1x client modules:
25 - compatible: "nvidia,tegra<chip>-mpe"
26 - reg: Physical base address and length of the controller's registers.
27 - interrupts: The interrupt outputs from the controller.
28 - clocks: Must contain one entry, for the module clock.
29 See ../clocks/clock-bindings.txt for details.
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
38 - compatible: "nvidia,tegra<chip>-vi"
39 - reg: Physical base address and length of the controller's registers.
40 - interrupts: The interrupt outputs from the controller.
41 - clocks: Must contain one entry, for the module clock.
42 See ../clocks/clock-bindings.txt for details.
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
48 - epp: encoder pre-processor
51 - compatible: "nvidia,tegra<chip>-epp"
52 - reg: Physical base address and length of the controller's registers.
53 - interrupts: The interrupt outputs from the controller.
54 - clocks: Must contain one entry, for the module clock.
55 See ../clocks/clock-bindings.txt for details.
56 - resets: Must contain an entry for each entry in reset-names.
57 See ../reset/reset.txt for details.
58 - reset-names: Must include the following entries:
61 - isp: image signal processor
64 - compatible: "nvidia,tegra<chip>-isp"
65 - reg: Physical base address and length of the controller's registers.
66 - interrupts: The interrupt outputs from the controller.
67 - clocks: Must contain one entry, for the module clock.
68 See ../clocks/clock-bindings.txt for details.
69 - resets: Must contain an entry for each entry in reset-names.
70 See ../reset/reset.txt for details.
71 - reset-names: Must include the following entries:
74 - gr2d: 2D graphics engine
77 - compatible: "nvidia,tegra<chip>-gr2d"
78 - reg: Physical base address and length of the controller's registers.
79 - interrupts: The interrupt outputs from the controller.
80 - clocks: Must contain one entry, for the module clock.
81 See ../clocks/clock-bindings.txt for details.
82 - resets: Must contain an entry for each entry in reset-names.
83 See ../reset/reset.txt for details.
84 - reset-names: Must include the following entries:
87 - gr3d: 3D graphics engine
90 - compatible: "nvidia,tegra<chip>-gr3d"
91 - reg: Physical base address and length of the controller's registers.
92 - clocks: Must contain an entry for each entry in clock-names.
93 See ../clocks/clock-bindings.txt for details.
94 - clock-names: Must include the following entries:
95 (This property may be omitted if the only clock in the list is "3d")
97 This MUST be the first entry.
98 - 3d2 (Only required on SoCs with two 3D clocks)
99 - resets: Must contain an entry for each entry in reset-names.
100 See ../reset/reset.txt for details.
101 - reset-names: Must include the following entries:
103 - 3d2 (Only required on SoCs with two 3D clocks)
105 - dc: display controller
108 - compatible: "nvidia,tegra<chip>-dc"
109 - reg: Physical base address and length of the controller's registers.
110 - interrupts: The interrupt outputs from the controller.
111 - clocks: Must contain an entry for each entry in clock-names.
112 See ../clocks/clock-bindings.txt for details.
113 - clock-names: Must include the following entries:
115 This MUST be the first entry.
117 - resets: Must contain an entry for each entry in reset-names.
118 See ../reset/reset.txt for details.
119 - reset-names: Must include the following entries:
122 Each display controller node has a child node, named "rgb", that represents
123 the RGB output associated with the controller. It can take the following
125 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
126 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
127 - nvidia,edid: supplies a binary EDID blob
128 - nvidia,panel: phandle of a display panel
130 - hdmi: High Definition Multimedia Interface
133 - compatible: "nvidia,tegra<chip>-hdmi"
134 - reg: Physical base address and length of the controller's registers.
135 - interrupts: The interrupt outputs from the controller.
136 - vdd-supply: regulator for supply voltage
137 - pll-supply: regulator for PLL
138 - clocks: Must contain an entry for each entry in clock-names.
139 See ../clocks/clock-bindings.txt for details.
140 - clock-names: Must include the following entries:
142 This MUST be the first entry.
144 - resets: Must contain an entry for each entry in reset-names.
145 See ../reset/reset.txt for details.
146 - reset-names: Must include the following entries:
150 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
151 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
152 - nvidia,edid: supplies a binary EDID blob
153 - nvidia,panel: phandle of a display panel
155 - tvo: TV encoder output
158 - compatible: "nvidia,tegra<chip>-tvo"
159 - reg: Physical base address and length of the controller's registers.
160 - interrupts: The interrupt outputs from the controller.
161 - clocks: Must contain one entry, for the module clock.
162 See ../clocks/clock-bindings.txt for details.
164 - dsi: display serial interface
167 - compatible: "nvidia,tegra<chip>-dsi"
168 - reg: Physical base address and length of the controller's registers.
169 - clocks: Must contain an entry for each entry in clock-names.
170 See ../clocks/clock-bindings.txt for details.
171 - clock-names: Must include the following entries:
173 This MUST be the first entry.
176 - resets: Must contain an entry for each entry in reset-names.
177 See ../reset/reset.txt for details.
178 - reset-names: Must include the following entries:
180 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
181 which pads are used by this DSI output and need to be calibrated. See also
182 ../mipi/nvidia,tegra114-mipi.txt.
185 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
186 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
187 - nvidia,edid: supplies a binary EDID blob
188 - nvidia,panel: phandle of a display panel
196 compatible = "nvidia,tegra20-host1x", "simple-bus";
197 reg = <0x50000000 0x00024000>;
198 interrupts = <0 65 0x04 /* mpcore syncpt */
199 0 67 0x04>; /* mpcore general */
200 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
201 resets = <&tegra_car 28>;
202 reset-names = "host1x";
204 #address-cells = <1>;
207 ranges = <0x54000000 0x54000000 0x04000000>;
210 compatible = "nvidia,tegra20-mpe";
211 reg = <0x54040000 0x00040000>;
212 interrupts = <0 68 0x04>;
213 clocks = <&tegra_car TEGRA20_CLK_MPE>;
214 resets = <&tegra_car 60>;
219 compatible = "nvidia,tegra20-vi";
220 reg = <0x54080000 0x00040000>;
221 interrupts = <0 69 0x04>;
222 clocks = <&tegra_car TEGRA20_CLK_VI>;
223 resets = <&tegra_car 100>;
228 compatible = "nvidia,tegra20-epp";
229 reg = <0x540c0000 0x00040000>;
230 interrupts = <0 70 0x04>;
231 clocks = <&tegra_car TEGRA20_CLK_EPP>;
232 resets = <&tegra_car 19>;
237 compatible = "nvidia,tegra20-isp";
238 reg = <0x54100000 0x00040000>;
239 interrupts = <0 71 0x04>;
240 clocks = <&tegra_car TEGRA20_CLK_ISP>;
241 resets = <&tegra_car 23>;
246 compatible = "nvidia,tegra20-gr2d";
247 reg = <0x54140000 0x00040000>;
248 interrupts = <0 72 0x04>;
249 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
250 resets = <&tegra_car 21>;
255 compatible = "nvidia,tegra20-gr3d";
256 reg = <0x54180000 0x00040000>;
257 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
258 resets = <&tegra_car 24>;
263 compatible = "nvidia,tegra20-dc";
264 reg = <0x54200000 0x00040000>;
265 interrupts = <0 73 0x04>;
266 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
267 <&tegra_car TEGRA20_CLK_PLL_P>;
268 clock-names = "dc", "parent";
269 resets = <&tegra_car 27>;
278 compatible = "nvidia,tegra20-dc";
279 reg = <0x54240000 0x00040000>;
280 interrupts = <0 74 0x04>;
281 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
282 <&tegra_car TEGRA20_CLK_PLL_P>;
283 clock-names = "dc", "parent";
284 resets = <&tegra_car 26>;
293 compatible = "nvidia,tegra20-hdmi";
294 reg = <0x54280000 0x00040000>;
295 interrupts = <0 75 0x04>;
296 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
297 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
298 clock-names = "hdmi", "parent";
299 resets = <&tegra_car 51>;
300 reset-names = "hdmi";
305 compatible = "nvidia,tegra20-tvo";
306 reg = <0x542c0000 0x00040000>;
307 interrupts = <0 76 0x04>;
308 clocks = <&tegra_car TEGRA20_CLK_TVO>;
313 compatible = "nvidia,tegra20-dsi";
314 reg = <0x54300000 0x00040000>;
315 clocks = <&tegra_car TEGRA20_CLK_DSI>,
316 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
317 clock-names = "dsi", "parent";
318 resets = <&tegra_car 48>;