1 =====================================================================
2 SEC 4 Device Tree Binding
3 Copyright (C) 2008-2011 Freescale Semiconductor Inc.
9 -Run Time Integrity Check (RTIC) Node
10 -Run Time Integrity Check (RTIC) Memory Node
11 -Secure Non-Volatile Storage (SNVS) Node
12 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
16 Accelerator and Assurance Module (CAAM).
18 =====================================================================
23 SEC 4 h/w can process requests from 2 types of sources.
24 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
25 2. Job Rings (HW interface between cores & SEC 4 registers).
27 High Speed Data Path Configuration:
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
30 such as the P4080. The number of simultaneous dequeues the QI can make is
31 equal to the number of Descriptor Controller (DECO) engines in a particular
32 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
33 dequeue from 5 subportals simultaneously.
35 Job Ring Data Path Configuration:
37 Each JR is located on a separate 4k page, they may (or may not) be made visible
38 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
39 up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
41 =====================================================================
46 Node defines the base address of the SEC 4 block.
47 This block specifies the address range of all global
48 configuration registers for the SEC 4 block. It
49 also receives interrupts from the Run Time Integrity Check
50 (RTIC) function within the SEC 4 block.
57 Definition: Must include "fsl,sec-v4.0". Also includes SEC
58 ERA versions (optional) with which the device is compatible.
63 Definition: A standard property. Defines the number of cells
64 for representing physical addresses in child nodes.
69 Definition: A standard property. Defines the number of cells
70 for representing the size of physical addresses in
75 Value type: <prop-encoded-array>
76 Definition: A standard property. Specifies the physical
77 address and length of the SEC4 configuration registers.
82 Value type: <prop-encoded-array>
83 Definition: A standard property. Specifies the physical address
84 range of the SEC 4.0 register space (-SNVS not included). A
85 triplet that includes the child address, parent address, &
90 Value type: <prop_encoded-array>
91 Definition: Specifies the interrupts generated by this
92 device. The value of the interrupts property
93 consists of one interrupt specifier. The format
94 of the specifier is defined by the binding document
95 describing the node's interrupt parent.
98 Usage: (required if interrupt property is defined)
100 Definition: A single <phandle> value that points
101 to the interrupt parent to which the child domain
104 Note: All other standard properties (see the ePAPR) are allowed
110 compatible = "fsl,sec-v4.0", "fsl,sec-era-v2.0";
111 #address-cells = <1>;
113 reg = <0x300000 0x10000>;
114 ranges = <0 0x300000 0x10000>;
115 interrupt-parent = <&mpic>;
119 =====================================================================
122 Child of the crypto node defines data processing interface to SEC 4
123 across the peripheral bus for purposes of processing
124 cryptographic descriptors. The specified address
125 range can be made visible to one (or more) cores.
126 The interrupt defined for this node is controlled within
127 the address range of this node.
132 Definition: Must include "fsl,sec-v4.0-job-ring"
136 Value type: <prop-encoded-array>
137 Definition: Specifies a two JR parameters: an offset from
138 the parent physical address and the length the JR registers.
141 Usage: optional-but-recommended
142 Value type: <prop-encoded-array>
144 Specifies the LIODN to be used in conjunction with
145 the ppid-to-liodn table that specifies the PPID to LIODN mapping.
146 Needed if the PAMU is used. Value is a 12 bit value
147 where value is a LIODN ID for this JR. This property is
148 normally set by boot firmware.
152 Value type: <prop_encoded-array>
153 Definition: Specifies the interrupts generated by this
154 device. The value of the interrupts property
155 consists of one interrupt specifier. The format
156 of the specifier is defined by the binding document
157 describing the node's interrupt parent.
160 Usage: (required if interrupt property is defined)
161 Value type: <phandle>
162 Definition: A single <phandle> value that points
163 to the interrupt parent to which the child domain
168 compatible = "fsl,sec-v4.0-job-ring";
169 reg = <0x1000 0x1000>;
171 interrupt-parent = <&mpic>;
176 =====================================================================
177 Run Time Integrity Check (RTIC) Node
179 Child node of the crypto node. Defines a register space that
180 contains up to 5 sets of addresses and their lengths (sizes) that
181 will be checked at run time. After an initial hash result is
182 calculated, these addresses are checked by HW to monitor any
183 change. If any memory is modified, a Security Violation is
184 triggered (see SNVS definition).
190 Definition: Must include "fsl,sec-v4.0-rtic".
195 Definition: A standard property. Defines the number of cells
196 for representing physical addresses in child nodes. Must
202 Definition: A standard property. Defines the number of cells
203 for representing the size of physical addresses in
204 child nodes. Must have a value of 1.
208 Value type: <prop-encoded-array>
209 Definition: A standard property. Specifies a two parameters:
210 an offset from the parent physical address and the length
215 Value type: <prop-encoded-array>
216 Definition: A standard property. Specifies the physical address
217 range of the SEC 4 register space (-SNVS not included). A
218 triplet that includes the child address, parent address, &
223 compatible = "fsl,sec-v4.0-rtic";
224 #address-cells = <1>;
226 reg = <0x6000 0x100>;
227 ranges = <0x0 0x6100 0xe00>;
230 =====================================================================
231 Run Time Integrity Check (RTIC) Memory Node
232 A child node that defines individual RTIC memory regions that are used to
233 perform run-time integrity check of memory areas that should not modified.
234 The node defines a register that contains the memory address &
235 length (combined) and a second register that contains the hash result
236 in big endian format.
241 Definition: Must include "fsl,sec-v4.0-rtic-memory".
245 Value type: <prop-encoded-array>
246 Definition: A standard property. Specifies two parameters:
247 an offset from the parent physical address and the length:
249 1. The location of the RTIC memory address & length registers.
250 2. The location RTIC hash result.
253 Usage: optional-but-recommended
254 Value type: <prop-encoded-array>
256 Specifies the HW address (36 bit address) for this region
257 followed by the length of the HW partition to be checked;
258 the address is represented as a 64 bit quantity followed
262 Usage: optional-but-recommended
263 Value type: <prop-encoded-array>
265 Specifies the LIODN to be used in conjunction with
266 the ppid-to-liodn table that specifies the PPID to LIODN
267 mapping. Needed if the PAMU is used. Value is a 12 bit value
268 where value is a LIODN ID for this RTIC memory region. This
269 property is normally set by boot firmware.
273 compatible = "fsl,sec-v4.0-rtic-memory";
274 reg = <0x00 0x20 0x100 0x80>;
276 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
279 =====================================================================
280 Secure Non-Volatile Storage (SNVS) Node
282 Node defines address range and the associated
283 interrupt for the SNVS function. This function
284 monitors security state information & reports
290 Definition: Must include "fsl,sec-v4.0-mon".
294 Value type: <prop-encoded-array>
295 Definition: A standard property. Specifies the physical
296 address and length of the SEC4 configuration
302 Definition: A standard property. Defines the number of cells
303 for representing physical addresses in child nodes. Must
309 Definition: A standard property. Defines the number of cells
310 for representing the size of physical addresses in
311 child nodes. Must have a value of 1.
315 Value type: <prop-encoded-array>
316 Definition: A standard property. Specifies the physical address
317 range of the SNVS register space. A triplet that includes
318 the child address, parent address, & length.
322 Value type: <prop_encoded-array>
323 Definition: Specifies the interrupts generated by this
324 device. The value of the interrupts property
325 consists of one interrupt specifier. The format
326 of the specifier is defined by the binding document
327 describing the node's interrupt parent.
330 Usage: (required if interrupt property is defined)
331 Value type: <phandle>
332 Definition: A single <phandle> value that points
333 to the interrupt parent to which the child domain
338 compatible = "fsl,sec-v4.0-mon";
339 reg = <0x314000 0x1000>;
340 ranges = <0 0x314000 0x1000>;
341 interrupt-parent = <&mpic>;
345 =====================================================================
346 Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
348 A SNVS child node that defines SNVS LP RTC.
353 Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
357 Value type: <prop-encoded-array>
358 Definition: A standard property. Specifies the physical
359 address and length of the SNVS LP configuration registers.
362 sec_mon_rtc_lp@314000 {
363 compatible = "fsl,sec-v4.0-mon-rtc-lp";
367 =====================================================================
370 crypto: crypto@300000 {
371 compatible = "fsl,sec-v4.0";
372 #address-cells = <1>;
374 reg = <0x300000 0x10000>;
375 ranges = <0 0x300000 0x10000>;
376 interrupt-parent = <&mpic>;
380 compatible = "fsl,sec-v4.0-job-ring";
381 reg = <0x1000 0x1000>;
382 interrupt-parent = <&mpic>;
387 compatible = "fsl,sec-v4.0-job-ring";
388 reg = <0x2000 0x1000>;
389 interrupt-parent = <&mpic>;
394 compatible = "fsl,sec-v4.0-job-ring";
395 reg = <0x3000 0x1000>;
396 interrupt-parent = <&mpic>;
401 compatible = "fsl,sec-v4.0-job-ring";
402 reg = <0x4000 0x1000>;
403 interrupt-parent = <&mpic>;
408 compatible = "fsl,sec-v4.0-rtic";
409 #address-cells = <1>;
411 reg = <0x6000 0x100>;
412 ranges = <0x0 0x6100 0xe00>;
415 compatible = "fsl,sec-v4.0-rtic-memory";
416 reg = <0x00 0x20 0x100 0x80>;
420 compatible = "fsl,sec-v4.0-rtic-memory";
421 reg = <0x20 0x20 0x200 0x80>;
425 compatible = "fsl,sec-v4.0-rtic-memory";
426 reg = <0x40 0x20 0x300 0x80>;
430 compatible = "fsl,sec-v4.0-rtic-memory";
431 reg = <0x60 0x20 0x500 0x80>;
436 sec_mon: sec_mon@314000 {
437 compatible = "fsl,sec-v4.0-mon";
438 reg = <0x314000 0x1000>;
439 ranges = <0 0x314000 0x1000>;
440 interrupt-parent = <&mpic>;
444 compatible = "fsl,sec-v4.0-mon-rtc-lp";
449 =====================================================================