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2 SEC 4 Device Tree Binding
3 Copyright (C) 2008-2011 Freescale Semiconductor Inc.
9 -Run Time Integrity Check (RTIC) Node
10 -Run Time Integrity Check (RTIC) Memory Node
11 -Secure Non-Volatile Storage (SNVS) Node
12 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
16 Accelerator and Assurance Module (CAAM).
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23 SEC 4 h/w can process requests from 2 types of sources.
24 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
25 2. Job Rings (HW interface between cores & SEC 4 registers).
27 High Speed Data Path Configuration:
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
30 such as the P4080. The number of simultaneous dequeues the QI can make is
31 equal to the number of Descriptor Controller (DECO) engines in a particular
32 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
33 dequeue from 5 subportals simultaneously.
35 Job Ring Data Path Configuration:
37 Each JR is located on a separate 4k page, they may (or may not) be made visible
38 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
39 up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
41 =====================================================================
46 Node defines the base address of the SEC 4 block.
47 This block specifies the address range of all global
48 configuration registers for the SEC 4 block. It
49 also receives interrupts from the Run Time Integrity Check
50 (RTIC) function within the SEC 4 block.
57 Definition: Must include "fsl,sec-v4.0"
62 Definition: A standard property. Defines the number of cells
63 for representing physical addresses in child nodes.
68 Definition: A standard property. Defines the number of cells
69 for representing the size of physical addresses in
74 Value type: <prop-encoded-array>
75 Definition: A standard property. Specifies the physical
76 address and length of the SEC4 configuration registers.
81 Value type: <prop-encoded-array>
82 Definition: A standard property. Specifies the physical address
83 range of the SEC 4.0 register space (-SNVS not included). A
84 triplet that includes the child address, parent address, &
89 Value type: <prop_encoded-array>
90 Definition: Specifies the interrupts generated by this
91 device. The value of the interrupts property
92 consists of one interrupt specifier. The format
93 of the specifier is defined by the binding document
94 describing the node's interrupt parent.
97 Usage: (required if interrupt property is defined)
99 Definition: A single <phandle> value that points
100 to the interrupt parent to which the child domain
103 Note: All other standard properties (see the ePAPR) are allowed
109 compatible = "fsl,sec-v4.0";
110 #address-cells = <1>;
112 reg = <0x300000 0x10000>;
113 ranges = <0 0x300000 0x10000>;
114 interrupt-parent = <&mpic>;
118 =====================================================================
121 Child of the crypto node defines data processing interface to SEC 4
122 across the peripheral bus for purposes of processing
123 cryptographic descriptors. The specified address
124 range can be made visible to one (or more) cores.
125 The interrupt defined for this node is controlled within
126 the address range of this node.
131 Definition: Must include "fsl,sec-v4.0-job-ring"
135 Value type: <prop-encoded-array>
136 Definition: Specifies a two JR parameters: an offset from
137 the parent physical address and the length the JR registers.
140 Usage: optional-but-recommended
141 Value type: <prop-encoded-array>
143 Specifies the LIODN to be used in conjunction with
144 the ppid-to-liodn table that specifies the PPID to LIODN mapping.
145 Needed if the PAMU is used. Value is a 12 bit value
146 where value is a LIODN ID for this JR. This property is
147 normally set by boot firmware.
151 Value type: <prop_encoded-array>
152 Definition: Specifies the interrupts generated by this
153 device. The value of the interrupts property
154 consists of one interrupt specifier. The format
155 of the specifier is defined by the binding document
156 describing the node's interrupt parent.
159 Usage: (required if interrupt property is defined)
160 Value type: <phandle>
161 Definition: A single <phandle> value that points
162 to the interrupt parent to which the child domain
167 compatible = "fsl,sec-v4.0-job-ring";
168 reg = <0x1000 0x1000>;
170 interrupt-parent = <&mpic>;
175 =====================================================================
176 Run Time Integrity Check (RTIC) Node
178 Child node of the crypto node. Defines a register space that
179 contains up to 5 sets of addresses and their lengths (sizes) that
180 will be checked at run time. After an initial hash result is
181 calculated, these addresses are checked by HW to monitor any
182 change. If any memory is modified, a Security Violation is
183 triggered (see SNVS definition).
189 Definition: Must include "fsl,sec-v4.0-rtic".
194 Definition: A standard property. Defines the number of cells
195 for representing physical addresses in child nodes. Must
201 Definition: A standard property. Defines the number of cells
202 for representing the size of physical addresses in
203 child nodes. Must have a value of 1.
207 Value type: <prop-encoded-array>
208 Definition: A standard property. Specifies a two parameters:
209 an offset from the parent physical address and the length
214 Value type: <prop-encoded-array>
215 Definition: A standard property. Specifies the physical address
216 range of the SEC 4 register space (-SNVS not included). A
217 triplet that includes the child address, parent address, &
222 compatible = "fsl,sec-v4.0-rtic";
223 #address-cells = <1>;
225 reg = <0x6000 0x100>;
226 ranges = <0x0 0x6100 0xe00>;
229 =====================================================================
230 Run Time Integrity Check (RTIC) Memory Node
231 A child node that defines individual RTIC memory regions that are used to
232 perform run-time integrity check of memory areas that should not modified.
233 The node defines a register that contains the memory address &
234 length (combined) and a second register that contains the hash result
235 in big endian format.
240 Definition: Must include "fsl,sec-v4.0-rtic-memory".
244 Value type: <prop-encoded-array>
245 Definition: A standard property. Specifies two parameters:
246 an offset from the parent physical address and the length:
248 1. The location of the RTIC memory address & length registers.
249 2. The location RTIC hash result.
252 Usage: optional-but-recommended
253 Value type: <prop-encoded-array>
255 Specifies the HW address (36 bit address) for this region
256 followed by the length of the HW partition to be checked;
257 the address is represented as a 64 bit quantity followed
261 Usage: optional-but-recommended
262 Value type: <prop-encoded-array>
264 Specifies the LIODN to be used in conjunction with
265 the ppid-to-liodn table that specifies the PPID to LIODN
266 mapping. Needed if the PAMU is used. Value is a 12 bit value
267 where value is a LIODN ID for this RTIC memory region. This
268 property is normally set by boot firmware.
272 compatible = "fsl,sec-v4.0-rtic-memory";
273 reg = <0x00 0x20 0x100 0x80>;
275 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
278 =====================================================================
279 Secure Non-Volatile Storage (SNVS) Node
281 Node defines address range and the associated
282 interrupt for the SNVS function. This function
283 monitors security state information & reports
289 Definition: Must include "fsl,sec-v4.0-mon".
293 Value type: <prop-encoded-array>
294 Definition: A standard property. Specifies the physical
295 address and length of the SEC4 configuration
301 Definition: A standard property. Defines the number of cells
302 for representing physical addresses in child nodes. Must
308 Definition: A standard property. Defines the number of cells
309 for representing the size of physical addresses in
310 child nodes. Must have a value of 1.
314 Value type: <prop-encoded-array>
315 Definition: A standard property. Specifies the physical address
316 range of the SNVS register space. A triplet that includes
317 the child address, parent address, & length.
321 Value type: <prop_encoded-array>
322 Definition: Specifies the interrupts generated by this
323 device. The value of the interrupts property
324 consists of one interrupt specifier. The format
325 of the specifier is defined by the binding document
326 describing the node's interrupt parent.
329 Usage: (required if interrupt property is defined)
330 Value type: <phandle>
331 Definition: A single <phandle> value that points
332 to the interrupt parent to which the child domain
337 compatible = "fsl,sec-v4.0-mon";
338 reg = <0x314000 0x1000>;
339 ranges = <0 0x314000 0x1000>;
340 interrupt-parent = <&mpic>;
344 =====================================================================
345 Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
347 A SNVS child node that defines SNVS LP RTC.
352 Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
356 Value type: <prop-encoded-array>
357 Definition: A standard property. Specifies the physical
358 address and length of the SNVS LP configuration registers.
361 sec_mon_rtc_lp@314000 {
362 compatible = "fsl,sec-v4.0-mon-rtc-lp";
366 =====================================================================
369 crypto: crypto@300000 {
370 compatible = "fsl,sec-v4.0";
371 #address-cells = <1>;
373 reg = <0x300000 0x10000>;
374 ranges = <0 0x300000 0x10000>;
375 interrupt-parent = <&mpic>;
379 compatible = "fsl,sec-v4.0-job-ring";
380 reg = <0x1000 0x1000>;
381 interrupt-parent = <&mpic>;
386 compatible = "fsl,sec-v4.0-job-ring";
387 reg = <0x2000 0x1000>;
388 interrupt-parent = <&mpic>;
393 compatible = "fsl,sec-v4.0-job-ring";
394 reg = <0x3000 0x1000>;
395 interrupt-parent = <&mpic>;
400 compatible = "fsl,sec-v4.0-job-ring";
401 reg = <0x4000 0x1000>;
402 interrupt-parent = <&mpic>;
407 compatible = "fsl,sec-v4.0-rtic";
408 #address-cells = <1>;
410 reg = <0x6000 0x100>;
411 ranges = <0x0 0x6100 0xe00>;
414 compatible = "fsl,sec-v4.0-rtic-memory";
415 reg = <0x00 0x20 0x100 0x80>;
419 compatible = "fsl,sec-v4.0-rtic-memory";
420 reg = <0x20 0x20 0x200 0x80>;
424 compatible = "fsl,sec-v4.0-rtic-memory";
425 reg = <0x40 0x20 0x300 0x80>;
429 compatible = "fsl,sec-v4.0-rtic-memory";
430 reg = <0x60 0x20 0x500 0x80>;
435 sec_mon: sec_mon@314000 {
436 compatible = "fsl,sec-v4.0-mon";
437 reg = <0x314000 0x1000>;
438 ranges = <0 0x314000 0x1000>;
439 interrupt-parent = <&mpic>;
443 compatible = "fsl,sec-v4.0-mon-rtc-lp";
448 =====================================================================