Pileus Git - ~andy/linux/blob - Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

   1 * Renesas R-Car Gen2 Clock Pulse Generator (CPG)
   2
   3 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
   4 and several fixed ratio dividers.
   5
   6 Required Properties:
   7
   8   - compatible: Must be one of
   9     - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
  10     - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
  11     - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
  12
  13   - reg: Base address and length of the memory resource used by the CPG
  14
  15   - clocks: Reference to the parent clock
  16   - #clock-cells: Must be 1
  17   - clock-output-names: The names of the clocks. Supported clocks are "main",
  18     "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
  19
  20
  21 Example
  22 -------
  23
  24         cpg_clocks: cpg_clocks@e6150000 {
  25                 compatible = "renesas,r8a7790-cpg-clocks",
  26                              "renesas,rcar-gen2-cpg-clocks";
  27                 reg = <0 0xe6150000 0 0x1000>;
  28                 clocks = <&extal_clk>;
  29                 #clock-cells = <1>;
  30                 clock-output-names = "main", "pll0, "pll1", "pll3",
  31                                      "lb", "qspi", "sdh", "sd0", "sd1", "z";
  32         };